dp83815.h

用于嵌入式系统的TCP/IP协议栈

#define DP_RFCR_RFADDR_SOPAS1   (ui32)0x0000000A /* secureOn password 1-0 */
#define DP_RFCR_RFADDR_SOPAS2   (ui32)0x0000000C /* secureOn password 3-2 */
#define DP_RFCR_RFADDR_SOPAS3   (ui32)0x0000000E /* secureOn password 5-4 */
#define DP_RFCR_RFADDR_FMEM_LO  (ui32)0x00000200 /* Rx filter memory start */
#define DP_RFCR_RFADDR_FMEM_HI  (ui32)0x000003FE /* Rx filter memory end */
#define DP_RFCR_ULM             (ui32)0x00080000 /* U/L bit mask */
#define DP_RFCR_UHEN            (ui32)0x00100000 /* unicast hash enable */
#define DP_RFCR_MHEN            (ui32)0x00200000 /* multicast hash enable */
#define DP_RFCR_AARP            (ui32)0x00400000 /* accept ARP packets */
#define DP_RFCR_APAT            (ui32)0x07800000 /* accept on pattern match */
#define DP_RFCR_APM             (ui32)0x08000000 /* accept on perfect match */
#define DP_RFCR_AAU             (ui32)0x10000000 /* accept all unicast */
#define DP_RFCR_AAM             (ui32)0x20000000 /* accept all multicast */
#define DP_RFCR_AAB             (ui32)0x40000000 /* accept all broadcast */
#define DP_RFCR_RFEN            (ui32)0x80000000 /* Rx filter enable */

/*
 * Recieve Filter/Match Data Register Bit Masks (DP_RFDR)
 *
 * Used to read and write internal recieve filter registers, the pattern
 * buffer memory and the hash table memory.
 */
#define DP_RFDR_RFDATA          (ui32)0x0000FFFF /* Recieve Filter data */
#define DP_RFDR_BMASK           (ui32)0x00030000 /* Byte Mask */

/*
 * Boot ROM Address Register Bit Masks (DP_BRAR)
 */
#define DP_BRAR_ADDR            (ui32)0x0000FFFF /* Boot ROM Address */
#define DP_BRAR_AUTOINC         (ui32)0x80000000 /* Auto-Increment */

/*
 * Boot ROM Data Register Bit Masks (DP_BRDR)
 */
#define DP_BRDR_DATA            (ui32)0xFFFFFFFF /* Boot ROM Data */

/*
 * Silicon Revision Register Bit Masks (DP_SRR)
 */
#define DP_SRR_MIN              (ui32)0x000000FF /* Minor Revision Level */
#define DP_SRR_MAJ              (ui32)0x0000FF00 /* Major Revision Level */
#define DP_SRR_MAJ_SHF          8               /* Shift bits */

/*
 * Management Information Base Control Register Bit Masks (DP_MIBC)
 *
 * Used to control access to the statistics block and the warning bits
 * and to control the collection of management info statistics.
 */
#define DP_MIBC_WRN             (ui32)0x00000001 /* Warning Tst Indicator (RO) */
#define DP_MIBC_FRZ             (ui32)0x00000002 /* Freeze All Counters */
#define DP_MIBC_ACLR            (ui32)0x00000004 /* Clear all Counters */
#define DP_MIBC_MIBS            (ui32)0x00000008 /* MIB Counter Strobe (TEST) */

/*
 * BMCR - (Internal Phy) Basic Mode Control Register
 */
#define DP_BMCR_COL_TST         (ui16)0x0080 /* Collision Test */
#define DP_BMCR_HDX             (ui16)0x0000 /* Half duplex mode */
#define DP_BMCR_FDX             (ui16)0x0100 /* Full duplex mode */
#define DP_BMCR_ANEG_RES        (ui16)0x0200 /* Restart Auto negotiation */
#define DP_BMCR_ISOLATE         (ui16)0x0400 /* Isolate */
#define DP_BMCR_PWRDWN          (ui16)0x0800 /* Power Down */
#define DP_BMCR_ANEG_EN         (ui16)0x3100 /* Auto Negotiation Enable */
#define DP_BMCR_SPD_100         (ui16)0x2000 /* Speed Select 100Mbps */
#define DP_BMCR_SPD_10          (ui16)0x0000 /* Speed Select 100Mbps */
#define DP_BMCR_LOOP            (ui16)0x4000 /* Loopback */
#define DP_BMCR_RESET           (ui16)0xB100 /* Reset */

/*
 * BMSR - (Internal Phy) Basic Mode Status Register
 */
#define DP_BMSR_XREG_ABLE       (ui16)0x0001 /* Extended Register Capability */
#define DP_BMSR_JABR_DET        (ui16)0x0002 /* Jabber Detected */
#define DP_BMSR_LNK_VALID       (ui16)0x0004 /* Valid Link Status */
#define DP_BMSR_AN_ABLE         (ui16)0x0008 /* Auto-Neg Ability */
#define DP_BMSR_REM_FLT         (ui16)0x0010 /* Remote Fault Detected */
#define DP_BMSR_AN_DONE         (ui16)0x0020 /* Auto Nego Complete */
#define DP_BMSR_PRS_ABLE        (ui16)0x0040 /* Preamble Supr Capable */
#define DP_BMSR_10_HD_ABLE      (ui16)0x0800 /* 10BASE-T Half Duplex Capable */
#define DP_BMSR_10_FD_ABLE      (ui16)0x1000 /* 10BASE-T Full Duplex Capable */
#define DP_BMSR_100_HD_ABLE     (ui16)0x2000 /* 100BASE-TX Half Duplex Capable */
#define DP_BMSR_100_FD_ABLE     (ui16)0x4000 /* 100BASE-TX Full Duplex Capable */
#define DP_BMSR_100T4_ABLE      (ui16)0x8000 /* 100BASE -T4 Capable */

/*
 * PHY Identifier Register #1
 */
#define DP_PHYIDR1_OUI_MSB      (ui16)0xFFFF /* OUI Most significant Bits */

/*
 * PHY Identifier Register #2
 */
#define DP_PHYIDR2_MDL_REV      (ui16)0x000F /* Model Revision number */
#define DP_PHYIDR2_VNDR_MDL     (ui16)0x03F0 /* Vendor Model Number */
#define DP_PHYIDR2_OUI_LSB      (ui16)0xFC00 /* OUI Last Significant Bits */

/*
 * Auto-Negotiation Advertisement Register
 *
 * Contains the advertised abilities of this device as they will be transmitted
 * to its link partner during Auto-Negotiation.
 */
#define DP_ANAR_SEL             (ui16)0x001F /* Protocol Selection Bits */
#define DP_ANAR_10T             (ui16)0x0020 /* 10BASE-T Support */
#define DP_ANAR_10_FD           (ui16)0x0040 /* 10BASE-T Full Duplex Support */
#define DP_ANAR_TX              (ui16)0x0080 /* 100BASE-TX Support */
#define DP_ANAR_TX_FD           (ui16)0x0100 /* 100BASE-TX Full Duplex Support */
#define DP_ANAR_T4              (ui16)0x0200 /* 100BASE-T4 Support */
#define DP_ANAR_PAUSE           (ui16)0x0400 /* Pause */
#define DP_ANAR_RF              (ui16)0x2000 /* Remote Fault */
#define DP_ANAR_NP              (ui16)0x8000 /* Next Page Indication */

/*
 * Auto-Negotiation Link Partner Ability Register
 *
 * Contains the advertised abilities of the Link Partner as recieved during
 * Auto Negotiation. The content changes after the successful autonegotiation
 * if Next-Pages are supported.
 */
#define DP_ANLPAR_SEL           (ui16)0x001F /* Protocol Selection Bits */
#define DP_ANLPAR_10T           (ui16)0x0020 /* 10BASE-T Support */
#define DP_ANLPAR_10_FD         (ui16)0x0040 /* 10BASE-T Full Duplex */
#define DP_ANLPAR_TX            (ui16)0x0080 /* 100BASE-TX Support */
#define DP_ANLPAR_TX_FD         (ui16)0x0100 /* 100BASE-TX Full Duplex */
#define DP_ANLPAR_T4            (ui16)0x0200 /* 100BASE-T4 Support */
#define DP_ANLPAR_RF            (ui16)0x2000 /* Remote Fault */
#define DP_ANLPAR_ACK           (ui16)0x4000 /* Acknowledge */
#define DP_ANLPAR_NP            (ui16)0x8000 /* Next Page Indication */

/*
 * Auto-Negotiation Expansion Register
 *
 * Contains additional Local device and Link Partner status info.
 */
#define DP_ANER_LP_AN_ABLE      (ui16)0x0001 /* Link Partner Auto Neg Able */
#define DP_ANER_PAGE_RX         (ui16)0x0002 /* Link Code Word Page Recvd */
#define DP_ANER_NP_ABLE         (ui16)0x0004 /* Next Page Able */
#define DP_ANER_LP_NP_ABLE      (ui16)0x0008 /* Link Partner NextPage Able */
#define DP_ANER_PDF             (ui16)0x0010 /* Parallel Detection Fault */

/*
 * Auto-Negotiation Next page Transmit Register
 *
 * Contains the next page Info sent by this device to its Link Partner
 * during Auto-Negotiation.
 */
#define DP_ANNPTR_CODE          (ui16)0x07FF /* Code Field */
#define DP_ANNPTR_TOG_TX        (ui16)0x0800 /* Toggle */
#define DP_ANNPTR_ACK2          (ui16)0x1000 /* Acknowledge2 */
#define DP_ANNPTR_MP            (ui16)0x2000 /* Message Page */
#define DP_ANNPTR_NP            (ui16)0x8000 /* Next Page Indication */

/*
 * PHY Status Register
 *
 * Provides a single location within the register set for quick access to
 * commonly accessed information
 */
#define DP_PHYSTS_LNK_VALID     (ui16)0x0001 /* Valid Link */
#define DP_PHYSTS_SPEED_10      (ui16)0x0002 /* 10 Mbps Mode */
#define DP_PHYSTS_FDX           (ui16)0x0004 /* Full Duplex Mode */
#define DP_PHYSTS_LOOP          (ui16)0x0008 /* Loopback Enabled */
#define DP_PHYSTS_ANEG_DONE     (ui16)0x0010 /* Auto-Neg Complete */
#define DP_PHYSTS_JABBER        (ui16)0x0020 /* Jabbler Detected */
#define DP_PHYSTS_REM_FAULT     (ui16)0x0040 /* Remote Fault Detected */
#define DP_PHYSTS_MII_INTR      (ui16)0x0080 /* MII Interrupt Pending */
#define DP_PHYSTS_LCWP_RX       (ui16)0x0100 /* Link Code Word Page Rx'd */
#define DP_PHYSTS_DSCRMBL_LCK   (ui16)0x0200 /* 100TX Descrambler Lock */
#define DP_PHYSTS_SIG_DET       (ui16)0x0400 /* 100TX Uncond Signal Detect */
#define DP_PHYSTS_FCSL          (ui16)0x0800 /* False Carrier Sense Latch */
#define DP_PHYSTS_POL_INV       (ui16)0x1000 /* Polarity status */
#define DP_PHYSTS_RX_ERR_LATCH  (ui16)0x2000 /* Received error latch */

/*
 * False Carrier Sense Counter Register
 *
 * provides info required to implement the "FalseCarriers" attribute within
 * the MAJ managed object class of Clause 30 of the IEEE 802.3u specification.
 */
#define DP_FCSCR_FCSCNT         (ui16)0x00FF /* False Carrier Event Counter */

/*
 * Receiver Error Counter Register
 *
 * Provides info required to implement the "SymbolErrorDuringCarrier" attribute
 * within  the PHY managed object class of Clause 30 of the IEEE 802.3u
 * specification.
 */
#define DP_RECR_RXERCNT         (ui16)0x00FF /* RX_ER counter */

/*
 * 100 Mb/s PCS Configuration and Status Register
 */
#define DP_PCSR_NRZI_BYP        (ui16)0x0004 /* NRZI bypass enable */
#define DP_PCSR_FRC_100_OK      (ui16)0x0020 /* force 100Mb/s good Link */
#define DP_PCSR_SD_OPT          (ui16)0x0100 /* signal detect option */
#define DP_PCSR_SD_F_B          (ui16)0x0200 /* signal detect force */
#define DP_PCSR_TQ_EN           (ui16)0x0400 /* 100Mbs True Quite Mode En */
#define DP_PCSR_FREE_CLK        (ui16)0x0800 /* receive clock */
#define DP_PCSR_BYP_4B5B        (ui16)0x1000 /* bypass 4B/5B Encoding */

/*
 * PHY Control Register
 */
#define DP_PHYCR_PHYADDR        (ui16)0x001F /* PHY address */
#define DP_PHYCR_LED_CFG        (ui16)0x0060 /* LED configuration */
#define DP_PHYCR_LED_CFG_10_HI  (ui16)0x0000 /* Speed10 HIGH */
#define DP_PHYCR_LED_CFG_10     (ui16)0x0020 /* Speed10 selected */
#define DP_PHYCR_LED_CFG_DPLXHI (ui16)0x0040 /* DPLX active HIGH */
#define DP_PHYCR_LED_CFG_DPLX   (ui16)0x0060 /* DPLX selected */
#define DP_PHYCR_PAUSE_PASS     (ui16)0x0080 /* pause compare pass */
#define DP_PHYCR_BP_STRETCH     (ui16)0x0100 /* bypass LED stretch */
#define DP_PHYCR_BIST_START     (ui16)0x0200 /* BIST start */
#define DP_PHYCR_BIST_PASS      (ui16)0x0400 /* BIST pass */
#define DP_PHYCR_PSR_15         (ui16)0x0800 /* BIST sequence sel PSR15 (PSR9) */

/*
 * 10Base-T Status/Control Register(10BTSCR)
 */
#define DP_TBTSCR_JABR_DIS      (ui16)0x0001 /* jabber disable */
#define DP_TBTSCR_HB_DIS        (ui16)0x0002 /* heartbeat disable */
#define DP_TBTSCR_LOW_SQL       (ui16)0x0004 /* reduced squelch enable */
#define DP_TBTSCR_AUTOPOL_DIS   (ui16)0x0008 /* auto polarity disable */
#define DP_TBTSCR_POL           (ui16)0x0010 /* 10Mb polarity status */
#define DP_TBTSCR_FRC_POL_COR   (ui16)0x0020 /* force 10Mb polarity correction */
#define DP_TBTSCR_FRC_10        (ui16)0x0040 /* force 10Mb good link */
#define DP_TBTSCR_LP_DIS        (ui16)0x0080 /* normal link pulse disable */
#define DP_TBTSCR_LB10_DIS      (ui16)0x0100 /* 10Base-T loopback disable */


/*
 * Transmit and Receive Descriptors
 *
 * DP83815 uses the same descriptor layout for both transmit and receive
 * descriptors.
 */
#define DP_DESC_SIZE            0x0C /* 3 words */

/* Descriptor Layout */

#define DP_DESC_LNK             0x00 /* Link field offset */
#define DP_DESC_CMDSTS          0x04 /* Command & status offset */
#define DP_DESC_BUFPTR          0x08 /* Buffer pointer offset */

/*
** DP_DESC_CMDSTS - Descriptor Command and Status Definitions
**
** Common Bit Definitions
*/
#define DP_DESC_CMDSTS_OWN          (ui32)(1 << 31) /* owner */
#define DP_DESC_CMDSTS_MORE         (1 << 30)   /* more descriptors */
#define DP_DESC_CMDSTS_INTR         (1 << 29)   /* interrupt */
#define DP_DESC_CMDSTS_OK           (1 << 27)   /* packet okay */
#define DP_DESC_CMDSTS_SIZE         0xFFF       /* data size */

/*
** Transmit Status Bit Definitions
*/
#define DP_DESC_CMDSTS_TX_TXA       (1 << 26)   /* Tx abort */
#define DP_DESC_CMDSTS_TX_TFU       (1 << 25)   /* Tx FIFO underrun */
#define DP_DESC_CMDSTS_TX_CRS       (1 << 24)   /* carrier sense lost */
#define DP_DESC_CMDSTS_TX_TD        (1 << 23)   /* transmit deferrals */
#define DP_DESC_CMDSTS_TX_ED        (1 << 22)   /* excessive deferrals */
#define DP_DESC_CMDSTS_TX_OWC       (1 << 21)   /* out of window collns */
#define DP_DESC_CMDSTS_TX_EC        (1 << 20)   /* excessive collisions */
#define DP_DESC_CMDSTS_TX_CCNT      (0xF << 16) /* collision Count */

/*
** Receive Status Bit Definitions
*/
#define DP_DESC_CMDSTS_RX_RXA       (1 << 26)   /* receive aborted */
#define DP_DESC_CMDSTS_RX_RXO       (1 << 25)   /* receive overrun */
#define DP_DESC_CMDSTS_RX_DEST      (3 << 23)   /* destination class */
#define DP_DESC_CMDSTS_RX_DEST_REJ  (0 << 23)   /*  packet rejected */
#define DP_DESC_CMDSTS_RX_DEST_UNI  (1 << 23)   /*  unicast packet */
#define DP_DESC_CMDSTS_RX_DEST_MC   (2 << 23)   /*  multicast packet */
#define DP_DESC_CMDSTS_RX_DEST_BC   (3 << 23)   /*  broadcast packet */
#define DP_DESC_CMDSTS_RX_LONG      (1 << 22)   /* long packet */
#define DP_DESC_CMDSTS_RX_RUNT      (1 << 21)   /* runt packet */
#define DP_DESC_CMDSTS_RX_ISE       (1 << 20)   /* invalid symbol error */
#define DP_DESC_CMDSTS_RX_CRCE      (1 << 19)   /* CRC error */
#define DP_DESC_CMDSTS_RX_FAE       (1 << 18)   /* frame align error */
#define DP_DESC_CMDSTS_RX_LBP       (1 << 17)   /* loopback packet */
#define DP_DESC_CMDSTS_RX_COL       (1 << 16)   /* collision */

#define DP_DESC_CMDSTS_TX_ERRORS    (DP_DESC_CMDSTS_TX_TXA | \
                                     DP_DESC_CMDSTS_TX_TFU | \
                                     DP_DESC_CMDSTS_TX_CRS | \
                                     DP_DESC_CMDSTS_TX_ED  | \
                                     DP_DESC_CMDSTS_TX_OWC | \
                                     DP_DESC_CMDSTS_TX_EC)

#define DP_DESC_CMDSTS_RX_ERRORS    (DP_DESC_CMDSTS_RX_LONG | \
                                     DP_DESC_CMDSTS_RX_RUNT | \
                                     DP_DESC_CMDSTS_RX_ISE  | \
                                     DP_DESC_CMDSTS_RX_CRCE | \
                                     DP_DESC_CMDSTS_RX_FAE)

#endif /* __DP83815_H__ */