dp83815.h

用于嵌入式系统的TCP/IP协议栈

/* dp83815.h -- National Semiconductor DP83815 Ethernet Controller Interface */
/* Changes for the Rev C of DP83815 have been included */

#ifndef __DP83815_H__
#define __DP83815_H__

#define DP_DEV_NAME        "National Semiconductor DP83815 PCI Ethernet"
#define DP_DRV_NAME        "dp83815"

/* PCI Confiugration Registers */

#undef  PCI_VENDOR_ID_NS_83815
#define PCI_VENDOR_ID_NS_83815  0x0020 /* DP83815 */

#define DP83815_PCI_IO_SIZE  256

/*
 * Operational Registers:
 * These registers are mapped either into PCI memory space or I/O space.
 */

/* MAC/BIU Registers */

#define DP_CR               0x00 /* Command Register */
#define DP_CFG              0x04 /* Configuration Register */
#define DP_MEAR             0x08 /* EEPROM Access Register */
#define DP_PTSCR            0x0C /* PCI Test Control Register */
#define DP_ISR              0x10 /* Intr Status Register */
#define DP_IMR              0x14 /* Intr Mask Register */
#define DP_IER              0x18 /* Intr Enable Register */
#define DP_TXDP             0x20 /* Tx Descriptor Pointer Register */
#define DP_TXCFG            0x24 /* Tx Configuration Register */
#define DP_RXDP             0x30 /* Rx Descriptor Pointer Register */
#define DP_RXCFG            0x34 /* Rx Configuration Register */
#define DP_WCSR             0x40 /* wake on LAN Control/Status Register */
#define DP_PCR              0x44 /* Pause Control/Status Register */
#define DP_RFCR             0x48 /* Rx Filter/Match Control Register */
#define DP_RFDR             0x4C /* Rx Filter/Match Data Register */
#define DP_BRAR             0x50 /* Boot ROM Address */
#define DP_BRDR             0x54 /* Boot ROM Data */
#define DP_SRR              0x58 /* Silicon Revision Register (RO) */
#define DP_MIBC             0x5C /* MIB Control Registor */
#define DP_MIB              0x60 /* MIB Data Register Base (RO) */

/* MIB Registers */

#define DP_MIB_RX_PKT_ERR   0x60 /* Pkts recvd with errors */
#define DP_MIB_RX_FCS_ERR   0x64 /* Pkts recvd with frame check seq errs */
#define DP_MIB_RX_MISS_PKT  0x68 /* Pkts missed due to FIFO  overruns*/
#define DP_MIB_RX_FA_ERR    0x6C /* Pkts recvd with frame alignment errs */
#define DP_MIB_RX_SYM_ERR   0x70 /* Pkts recvd with symbol errs */
#define DP_MIB_RX_LONG_FRM  0x74 /* Pkts > 1518 bytes */
#define DP_MIB_TXSQE_ERR    0x78 /* Loss of coll. heartbeat on Tx */

/* Internal Phy Registers */

#define DP_BMCR             0x80 /* Basic Mode Control Register */
#define DP_BMSR             0x84 /* Basic Mode Status Register (RO) */
#define DP_PHYIDR1          0x88 /* PHY Identifier Register #1 (RO) */
#define DP_PHYIDR2          0x8C /* PHY Identifier Register #2 (RO) */
#define DP_ANAR             0x90 /* Auto-Nego Advertisment Reg */
#define DP_ANLPAR           0x94 /* Auto-Nego Link Partner Ability Reg */
#define DP_ANER             0x98 /* Auto-Negotiation Expansion Reg */
#define DP_ANNPTR           0x9C /* Auto-Negotiation Next Page TX */
#define DP_PHYSTS           0xC0 /* PHY Status Register (RO) */
#define DP_FCSCR            0xD0 /* False Carrier Sense Counter Reg */
#define DP_RECR             0xD4 /* Recv Error Counter Register */
#define DP_PHYCR            0xE4 /* PHY Control Register */
#define DP_TBTSCR           0xE8 /* 10Base-TStatus/Control Reg */

/* New Phy registers and their bit mask values for Rev 3 */

#define DP_PGSEL            0xCC
#define DP_TSTDAT           0xFC
#define DP_DSPCFG           0xF4
#define DP_SDCFG            0xF8

#if 0
#define DP_PGSEL_VAL            (ui16)0x0001 /* */
#define DP_DSPCFG_VAL           (ui16)0x5040 /* Load/Kill C2 */
#define DP_SDCFG_VAL            (ui16)0x008C /* Raise SD off, from 4 to C */
#define DP_TSTDAT_VAL           (ui16)0x0000 /* Set value for C2 */
#define DP_PHYCR_PMDCSR_VAL     (ui16)0x189C /* DC Speed = 01 */
#endif

/*
** Command Register Bit Masks (DP_CR)
**
** Used for issuing commands to DP83815. A global software reset along
** with individual reset and enable/disable switches for transmitter and
** receiver are provided here.
*/
#define DP_CR_TXE               (1 << 0)        /* Transmit Enable */
#define DP_CR_TXD               (1 << 1)        /* Transmit Disable */
#define DP_CR_RXE               (1 << 2)        /* Receiver Enable */
#define DP_CR_RXD               (1 << 3)        /* Receiver Disable */
#define DP_CR_TXR               (1 << 4)        /* Transmit Reset */
#define DP_CR_RXR               (1 << 5)        /* Receiver Reset */
#define DP_CR_SWI               (1 << 7)        /* Software Interrupt */
#define DP_CR_RST               (1 << 8)        /* Reset */

/*
** Configuration and Media Status Register Bit Masks (DP_CFG)
**
** Allows configuration of a various device and phy options, and provides
** phy status information.
*/
#define DP_CFG_BEM              (1 << 0)        /* Big Endian Mode (BM xfers) */
#define DP_CFG_BROM_DIS         (1 << 2)        /* Disable Boot ROM interface */
#define DP_CFG_PESEL            (1 << 3)        /* Parity Err Det (BM xfer) */
#define DP_CFG_EXD              (1 << 4)        /* Excessv Deferl Tmr disbl */
#define DP_CFG_POW              (1 << 5)        /* Prog Out of Window Timer */
#define DP_CFG_SB               (1 << 6)        /* Single Back-off */
#define DP_CFG_REQALG           (1 << 7)        /* PCI Bus Request Algorithm */
#define DP_CFG_EUPHCOMP         (1 << 8)        /* DP83810 Descriptor Compat */
#define DP_CFG_PHY_DIS          (1 << 9)        /* Disable internal Phy */
#define DP_CFG_PHY_RST          (1 << 10)       /* Reset internal Phy */
#define DP_CFG_ANEG_SEL_10_HD   (0 << 13)       /*  Force 10Mb Half duplex */
#define DP_CFG_ANEG_SEL_100_HD  (2 << 13)       /*  Force 100Mb Half duplex */
#define DP_CFG_ANEG_SEL_10_FD   (4 << 13)       /*  Force 10Mb Full duplex */
#define DP_CFG_ANEG_SEL_100_FD  (6 << 13)       /*  Force 100Mb Full duplex */
#define DP_CFG_ANEG_SEL_10_XD   (1 << 13)       /*  Nego 10Mb Half/Full dplx */
#define DP_CFG_ANEG_SEL_ALL_HD  (3 << 13)       /*  Nego 10/100 Half duplex */
#define DP_CFG_ANEG_SEL_100_XD  (5 << 13)       /*  Nego 100 Half/Full duplex */
#define DP_CFG_ANEG_SEL_ALL_XD  (7 << 13)       /*  nego 10/100 Half/Full dplx*/
#define DP_CFG_PAUSE_ADV        (1 << 16)       /* Strap for pause capable */
#define DP_CFG_PINT_ACEN        (1 << 17)       /* Phy Intr Auto Clr Enable */
#define DP_CFG_PHY_CFG          (0x3F << 18)    /* Phy Configuration */
#define DP_CFG_ANEG_DN          (1 << 27)       /* Auto-negotiation Done */
#define DP_CFG_POL              (1 << 28)       /* 10Mb Polarity Indication */
#define DP_CFG_FDUP             (1 << 29)       /* Full Duplex */
#define DP_CFG_SPEED100         (1 << 30)       /* Speed 100Mb */
#define DP_CFG_LNKSTS           (ui32)(1 << 31) /* Link status */

/*
 * EEPROM Access Register Bit Masks (DP_MEAR)
 *
 * Provides an interface for software access to the NMC9306 style EEPROM.  The
 * default values given assume that the EEDO line has a pullup resistor to
 * VDD.
 */
#define DP_MEAR_EEDI            (ui32)0x00000001 /* EEPROM data in */
#define DP_MEAR_EEDO            (ui32)0x00000002 /* EEPROM data out */
#define DP_MEAR_EECLK           (ui32)0x00000004 /* EEPROM Serial Clock */
#define DP_MEAR_EESEL           (ui32)0x00000008 /* EEPROM Chip Select */

/*
 * PCI Test Control Register Bit Masks (DP_PTSCR)
 */
#define DP_PTSCR_EEBIST_FAIL    (ui32)0x00000001 /* EE BIST Fail Indication */
#define DP_PTSCR_EEBIST_EN      (ui32)0x00000002 /* Enable  EEPROM BIST */
#define DP_PTSCR_EELOAD_EN      (ui32)0x00000004 /* Enable EEPROM Load */
#define DP_PTSCR_RBIST_RXFFAIL  (ui32)0x00000008 /* RX Filter RAM BIST Fail */
#define DP_PTSCR_RBIST_TXFAIL   (ui32)0x00000010 /* TX FiFO Fail */
#define DP_PTSCR_RBIST_RXFAIL   (ui32)0x00000020 /* RX FIFO BIST Fail */
#define DP_PTSCR_RBIST_ACT      (ui32)0x00000040 /* SRAM BIST Active*/
#define DP_PTSCR_RBIST_EN       (ui32)0x00000080 /* SRAM BIST Enable */
#define DP_PTSCR_RBIST_MODE     (ui32)0x00000100 /* SRAM BIST Mode */
#define DP_PTSCR_RBIST_CLKD     (ui32)0x00000200 /* SRAM BIST Clock */
#define DP_PTSCR_RBIST_RST      (ui32)0x00000400 /* SRAM BIST Reset */
#define DP_PTSCR_RESVD          (ui32)0x00001000 /* Reserved -- Must be 1 */

/*
** Interrupt Status Register Bit Masks (DP_ISR)
**
** Indicates interrupt source when the INTA pin goes active. Enabling
** corresponding IMR bits allows bits in this reg to produce interrupts.
** ISR reflects all pending interrupts regardless of the status of IMR.
**
**
** Interrupt Mask Register Bit Masks (DP_IMR)
**
** Interrupts are enabled by setting the appropriate bit-mask.
*/
#define DP_INT_RXOK             (1 << 0)        /* Rx okay */
#define DP_INT_RXDESC           (1 << 1)        /* Rx descriptor */
#define DP_INT_RXERR            (1 << 2)        /* Rx packet error */
#define DP_INT_RXEARLY          (1 << 3)        /* Rx early threshold */
#define DP_INT_RXIDLE           (1 << 4)        /* Rx idle */
#define DP_INT_RXORN            (1 << 5)        /* Rx overrun */
#define DP_INT_TXOK             (1 << 6)        /* Tx packet okay */
#define DP_INT_TXDESC           (1 << 7)        /* Tx descriptor */
#define DP_INT_TXERR            (1 << 8)        /* Tx packet error */
#define DP_INT_TXIDLE           (1 << 9)        /* Tx idle */
#define DP_INT_TXURN            (1 << 10)       /* Tx underrun */
#define DP_INT_MIB              (1 << 11)       /* MIB service */
#define DP_INT_SWI              (1 << 12)       /* software interrupt */
#define DP_INT_PME              (1 << 13)       /* power management event */
#define DP_INT_PHY              (1 << 14)       /* phy interrupt */
#define DP_INT_HIBERR           (1 << 15)       /* high bits error set */
#define DP_INT_RXSOVR           (1 << 16)       /* Rx status FIFO overrun */
#define DP_INT_RTABT            (1 << 20)       /* recieved target abort */
#define DP_INT_RMABT            (1 << 21)       /* recieved master abort */
#define DP_INT_SSERR            (1 << 22)       /* signaled system error */
#define DP_INT_DPERR            (1 << 23)       /* detected parity error */
#define DP_INT_RXRCMP           (1 << 24)       /* receive reset complete */
#define DP_INT_TXRCMP           (1 << 25)       /* transmit reset complete */

/*
** Interrupt Enable Register Bit Masks (DP_IER)
**
** Enable or disable DP chip interrupts
*/
#define DP_IER_IE               (1 << 0)        /* Interrupt Enable */
#define DP_IER_ID               (0 << 0)        /* Interrupt Disable */

/*
** Transmit Configuration Register Bit Masks (DP_TXCFG)
*/
#define DP_TXCFG_CSI            (ui32)(1 << 31) /* carrier sense ignore */
#define DP_TXCFG_HBI            (1 << 30)       /* heartBeat ignore */
#define DP_TXCFG_ATP            (1 << 28)       /* auto transmit pad */
#define DP_TXCFG_MXDMA_128      (0 << 20)       /* 128 32-bit words */
#define DP_TXCFG_MXDMA_1        (1 << 20)       /* 1 32-bit word */
#define DP_TXCFG_MXDMA_2        (2 << 20)       /* 2 32-bit words */
#define DP_TXCFG_MXDMA_4        (3 << 20)       /* 4 32-bit words */
#define DP_TXCFG_MXDMA_8        (4 << 20)       /* 8 32-bit words */
#define DP_TXCFG_MXDMA_16       (5 << 20)       /* 16 32-bit words */
#define DP_TXCFG_MXDMA_32       (6 << 20)       /* 32 32-bit words */
#define DP_TXCFG_MXDMA_64       (7 << 20)       /* 64 32-bit words */
#define DP_TXCFG_FLTH_SET(x)    (((x) & 0x3F) << 8) /* fill threshold */
#define DP_TXCFG_DRTH_SET(x)    ((x) & 0x3F)    /* Tx drain threshold */

/*
** Recieve Configuration Register Bit Masks (DP_RXCFG)
*/
#define DP_RXCFG_DRTH_SET(x)    (((x) << 1) & 0x3E) /* Rx drain threshold */
#define DP_RXCFG_MXDMA_128      (0 << 20)       /* 128 32-bit words */
#define DP_RXCFG_MXDMA_1        (1 << 20)       /* 1 32-bit words */
#define DP_RXCFG_MXDMA_2        (2 << 20)       /* 2 32-bit words */
#define DP_RXCFG_MXDMA_4        (3 << 20)       /* 4 32-bit words */
#define DP_RXCFG_MXDMA_8        (4 << 20)       /* 8 32-bit words */
#define DP_RXCFG_MXDMA_16       (5 << 20)       /* 16 32-bit words */
#define DP_RXCFG_MXDMA_32       (6 << 20)       /* 32 32-bit words */
#define DP_RXCFG_MXDMA_64       (7 << 20)       /* 64 32-bit words */
#define DP_RXCFG_ALP            (1 << 27)       /* accept long packets */
#define DP_RXCFG_ATX            (1 << 28)       /* accept tx packets */
#define DP_RXCFG_ARP            (1 << 30)       /* accept runt packets */
#define DP_RXCFG_AEP            (1 << 31)       /* accept rx errors */

/*
** Wake Command/status Register Bit Masks (DP_WCSR)
**
** Used to configure/control and monitor DP83815 Wake On LAN Logic. The
** Wake On LAN logic is used to monitor the incoming packet stream while
** in low-power state, and provide a wake event to the system if desired
** packet type, contents, or link change are detected.
*/
#define DP_WCSR_WKPHY           (ui32)0x00000001 /* wake on phy interrupt */
#define DP_WCSR_WKUCP           (ui32)0x00000002 /* wake on unicast */
#define DP_WCSR_WKMCP           (ui32)0x00000004 /* wake on multicast */
#define DP_WCSR_WKBCP           (ui32)0x00000008 /* wake on broadcast */
#define DP_WCSR_WKARP           (ui32)0x00000010 /* wake on ARP */
#define DP_WCSR_WKPAT0          (ui32)0x00000020 /* wake on pattern 0 match */
#define DP_WCSR_WKPAT1          (ui32)0x00000040 /* wake on pattern 1 match */
#define DP_WCSR_WKPAT2          (ui32)0x00000080 /* wake on pattern 2 match */
#define DP_WCSR_WKPAT3          (ui32)0x00000100 /* wake on pattern 3 match */
#define DP_WCSR_WKMAG           (ui32)0x00000200 /* wake on magic Packet */
#define DP_WCSR_MPSOE           (ui32)0x00000400 /* magic packet secureOn enbl */
#define DP_WCSR_SOHACK          (ui32)0x00200000 /* secureOn hack attempt */
#define DP_WCSR_PHYINT          (ui32)0x00400000 /* phy interrupt */
#define DP_WCSR_UCASTR          (ui32)0x00800000 /* unicast recieved */
#define DP_WCSR_MCASTR          (ui32)0x01000000 /* multicast recieved */
#define DP_WCSR_BCASTR          (ui32)0x02000000 /* broadcast recieved */
#define DP_WCSR_ARPR            (ui32)0x04000000 /* ARP recieved */
#define DP_WCSR_PATM0           (ui32)0x08000000 /* pattern 0 match */
#define DP_WCSR_PATM1           (ui32)0x10000000 /* pattern 1 match */
#define DP_WCSR_PATM2           (ui32)0x20000000 /* pattern 2 match */
#define DP_WCSR_PATM3           (ui32)0x40000000 /* pattern 3 match */
#define DP_WCSR_MPR             (ui32)0x80000000 /* magic packet recieved */

/*
 * Pause Control/Status Register Bit Masks (DP_PCR)
 *
 * Used to control and monitor the DP 83815 Pause Frame reception logic.
 * The Pause frame reception logic is used to accept 802.3x Pause frames,
 * extract the pause length value, and initiate a TXMAV pause interval of
 * the specified number of slot times.
 */
#define DP_PCR_PAUSE_CNT        (ui32)0x0000FFFF /* pause counter value */
#define DP_PCR_MLD_EN           (ui32)0x00010000 /* manual load enable */
#define DP_PCR_PSNEG            (ui32)0x00200000 /* pause negotiated */
#define DP_PCR_PS_RCVD          (ui32)0x00400000 /* pause frame recieved */
#define DP_PCR_PS_ACT           (ui32)0x00800000 /* pause active */
#define DP_PCR_PS_DA            (ui32)0x20000000 /* pause on DA */
#define DP_PCR_PS_MCAST         (ui32)0x40000000 /* pause on multicast */
#define DP_PCR_PSEN             (ui32)0x80000000 /* pause enable */

/*
 * Recieve Filter/Match Control Register Bit Masks (DP_RFCR)
 *
 * Used to control and configure the DP83815 Recieve Filter Control logic.
 * The RFC logic is used to configure destination address filtering of incoming
 * packets.
 */
#define DP_RFCR_RFADDR          (ui32)0x000003FF /* Rx filter extended RegAdd */
#define DP_RFCR_RFADDR_PMATCH1  (ui32)0x00000000 /* perfect match octets 1-0 */
#define DP_RFCR_RFADDR_PMATCH2  (ui32)0x00000002 /* perfect match octets 3-2 */
#define DP_RFCR_RFADDR_PMATCH3  (ui32)0x00000004 /* perfect match octets 5-4 */
#define DP_RFCR_RFADDR_PCOUNT1  (ui32)0x00000006 /* pattern count 1-0 */
#define DP_RFCR_RFADDR_PCOUNT2  (ui32)0x00000008 /* pattern count 3-2 */