📄 44binit.lst
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ARM Macro Assembler Page 1
1 00000000 ; ******************************************************
*
2 00000000 ; * NAME : 44BINIT.S *
3 00000000 ; * Description: *
4 00000000 ; * C start up codes *
5 00000000 ; * Configure memory, Initialize ISR ,stacks *
6 00000000 ; * Initialize C-variables *
7 00000000 ; * Fill zeros into zero-initialized C-variables *
8 00000000 ; ******************************************************
*
9 00000000
10 00000000 INCLUDE option.s
1 00000000 ;**********OPTIONS*******************************
2 00000000 ;_RAM_STARTADDRESS EQU 0xc100000
3 00000000 0C7FFF00
_ISR_STARTADDRESS
EQU 0xc7fff00 ;GCS6:64M DRAM/SDRAM
4 00000000 ;_ISR_STARTADDRESS EQU 0xc1fff00 ;GCS6:16M DRAM
5 00000000
6 00000000
7 00000000 ;BUSWIDTH; 16,32
8 00000000 GBLA BUSWIDTH
9 00000000 00000010
BUSWIDTH
SETA 16
10 00000000
11 00000000
12 00000000 ;"DRAM","SDRAM"
13 00000000 GBLS BDRAMTYPE
14 00000000 SDRAM BDRAMTYPE
SETS "SDRAM"
15 00000000
16 00000000
17 00000000
18 00000000 ;This value has to be TRUE on ROM program.
19 00000000 ;This value has to be FALSE in RAM program.
20 00000000 GBLL PLLONSTART
21 00000000 TRUE
PLLONSTART
SETL {TRUE}
22 00000000
23 00000000 GBLA PLLCLK
24 00000000 02625A00
PLLCLK SETA 40000000
25 00000000
26 00000000 [ PLLCLK = 40000000
27 00000000 00000048
M_DIV EQU 0x48 ;Fin=10MHz Fout=40MHz
28 00000000 00000003
P_DIV EQU 0x3
29 00000000 00000002
S_DIV EQU 0x2
30 00000000 ]
31 00000000
32 00000000 [ PLLCLK = 50000000
36 ]
37 00000000
38 00000000 [ PLLCLK = 60000000
42 ]
ARM Macro Assembler Page 2
43 00000000
44 00000000 [ PLLCLK = 66000000
48 ]
49 00000000
50 00000000 [ PLLCLK = 75000000
54 ]
55 00000000 ;************************************************
56 00000000 END
11 00000000 INCLUDE memcfg.s
1 00000000 ;**********MEMORY CONTROL PARAMETERS********************
***********
2 00000000 ;When MCLK=66MHz,1clk=0.0152us=15.2ns
3 00000000 ;Bank 0 parameter for Monitor Flash Rom
4 00000000 GBLS BDRAMTYPE
5 00000000 SDRAM BDRAMTYPE
SETS "SDRAM"
6 00000000 00000000
B0_Tacs EQU 0x0 ;0clk
7 00000000 00000000
B0_Tcos EQU 0x0 ;0clk
8 00000000 00000006
B0_Tacc EQU 0x6 ;10clk
9 00000000 00000000
B0_Tcoh EQU 0x0 ;0clk
10 00000000 00000000
B0_Tah EQU 0x0 ;0clk
11 00000000 00000000
B0_Tacp EQU 0x0 ;0clk
12 00000000 00000000
B0_PMC EQU 0x0 ;normal(1data)
13 00000000
14 00000000 ;Bank 1 parameter for USB PDIUSBD12(待定)
15 00000000 00000003
B1_Tacs EQU 0x3 ;4clk
16 00000000 00000003
B1_Tcos EQU 0x3 ;4clk
17 00000000 00000007
B1_Tacc EQU 0x7 ;14clk
18 00000000 00000003
B1_Tcoh EQU 0x3 ;4clk
19 00000000 00000003
B1_Tah EQU 0x3 ;4clk
20 00000000 00000003
B1_Tacp EQU 0x3 ;6clk
21 00000000 00000000
B1_PMC EQU 0x0 ;normal(1data)
22 00000000
23 00000000 ;Bank 2 parameter for IDE
24 00000000 00000003
B2_Tacs EQU 0x3 ;4clk
25 00000000 00000004
B2_Tcos EQU 0x4 ;4clk
26 00000000 00000006
B2_Tacc EQU 0x6 ;12clk
27 00000000 00000003
B2_Tcoh EQU 0x3 ;4clk
28 00000000 00000003
B2_Tah EQU 0x3 ;4clk
29 00000000 00000003
ARM Macro Assembler Page 3
B2_Tacp EQU 0x3 ;6clk
30 00000000 00000000
B2_PMC EQU 0x0 ;normal(1data)
31 00000000
32 00000000 ;Bank 3 parameter for NET RTL8019AS
33 00000000 00000003
B3_Tacs EQU 0x3 ;(Address set-up before nGCS
n)
34 00000000 00000003
B3_Tcos EQU 0x3 ;(Chip selection set-up nOE)
35 00000000 00000007
B3_Tacc EQU 0x7 ;14clk(Access cycle)
36 00000000 00000003
B3_Tcoh EQU 0x3 ;(Chip selection hold on nOE
)
37 00000000 00000003
B3_Tah EQU 0x3 ;(Address holding time after
nGCSn)
38 00000000 00000003
B3_Tacp EQU 0x3 ;(Page mode access cycle @ P
age mode)
39 00000000 00000000
B3_PMC EQU 0x0 ;normal(1data)
40 00000000
41 00000000 ;Bank 4 parameter
42 00000000 00000003
B4_Tacs EQU 0x3 ;4clk
43 00000000 00000003
B4_Tcos EQU 0x3 ;4clk
44 00000000 00000007
B4_Tacc EQU 0x7 ;14clk
45 00000000 00000003
B4_Tcoh EQU 0x3 ;4clk
46 00000000 00000003
B4_Tah EQU 0x3 ;4clk
47 00000000 00000003
B4_Tacp EQU 0x3 ;6clk
48 00000000 00000000
B4_PMC EQU 0x0 ;normal(1data)
49 00000000
50 00000000 ;Bank 5 parameter
51 00000000 00000003
B5_Tacs EQU 0x3 ;4clk
52 00000000 00000003
B5_Tcos EQU 0x3 ;4clk
53 00000000 00000007
B5_Tacc EQU 0x7 ;14clk
54 00000000 00000003
B5_Tcoh EQU 0x3 ;4clk
55 00000000 00000003
B5_Tah EQU 0x3 ;4clk
56 00000000 00000003
B5_Tacp EQU 0x3 ;6clk
57 00000000 00000000
B5_PMC EQU 0x0 ;normal(1data)
58 00000000
59 00000000 ;Bank 6(if SROM) parameter
60 00000000 ;B6_Tacs EQU 0x3 ;4clk
ARM Macro Assembler Page 4
61 00000000 ;B6_Tcos EQU 0x3 ;4clk
62 00000000 ;B6_Tacc EQU 0x7 ;14clk
63 00000000 ;B6_Tcoh EQU 0x3 ;4clk
64 00000000 ;B6_Tah EQU 0x3 ;4clk
65 00000000 ;B6_Tacp EQU 0x3 ;6clk
66 00000000 ;B6_PMC EQU 0x0 ;normal(1data)
67 00000000
68 00000000 ;Bank 7(if SROM) parameter
69 00000000 ;B7_Tacs EQU 0x3 ;4clk
70 00000000 ;B7_Tcos EQU 0x3 ;4clk
71 00000000 ;B7_Tacc EQU 0x7 ;14clk
72 00000000 ;B7_Tcoh EQU 0x3 ;4clk
73 00000000 ;B7_Tah EQU 0x3 ;4clk
74 00000000 ;B7_Tacp EQU 0x3 ;6clk
75 00000000 ;B7_PMC EQU 0x0 ;normal(1data)
76 00000000
77 00000000 ;Bank 6 parameter
78 00000000 [ BDRAMTYPE="DRAM" ;MT=01(FP DRAM) or 10(E
DO DRAM)
85 00000000 00000003
B6_MT EQU 0x3 ;SDRAM
86 00000000 00000000
B6_Trcd EQU 0x0 ;2clk
87 00000000 00000000
B6_SCAN EQU 0x0 ;8bit
88 00000000 ]
89 00000000
90 00000000 ;Bank 7 parameter
91 00000000 [ BDRAMTYPE="DRAM" ;MT=01(FP DRAM) or 10(E
DO DRAM)
98 00000000 00000003
B7_MT EQU 0x3 ;SDRAM
99 00000000 00000000
B7_Trcd EQU 0x0 ;2clk
100 00000000 00000000
B7_SCAN EQU 0x0 ;8bit
101 00000000 ]
102 00000000
103 00000000 ;REFRESH parameter
104 00000000 00000001
REFEN EQU 0x1 ;Refresh enable
105 00000000 00000000
TREFMD EQU 0x0 ;CBR(CAS before RAS)/Auto re
fresh
106 00000000 00000002
Trp EQU 0x2 ;2clk 0x1 ;3clk --zq
107 00000000 00000001
Trc EQU 0x1 ;5clk
108 00000000 00000002
Tchr EQU 0x2 ;3clk
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