armperip.xml

These patch files are supplied as part of ADS 1.2.1.

     <cpreg cp="15" crn="2" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>8</width>
     <display>CP15Cacheable</display>
  </register>
  <register>
     <name>Bufferable</name>
     <description>Bufferable</description>
     <cpreg cp="15" crn="3" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>8</width>
     <display>CP15Bufferable</display>
  </register>
  <register>
     <name>Protection</name>
     <description>Protection</description>
     <cpreg cp="15" crn="5" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>16</width>
     <display>CP15Protection</display>
  </register>
  <register>
     <name>Region0</name>
     <bank>Protection Regions</bank>
     <description>Memory area 0 definition</description>
     <cpreg cp="15" crn="6" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Region</display>
  </register>
  <register>
     <name>Region1</name>
     <bank>Protection Regions</bank>
     <description>Memory area 1 definition</description>
     <cpreg cp="15" crn="6" crm="1" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Region</display>
  </register>
  <register>
     <name>Region2</name>
     <bank>Protection Regions</bank>
     <description>Memory area 2 definition</description>
     <cpreg cp="15" crn="6" crm="2" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Region</display>
  </register>
  <register>
     <name>Region3</name>
     <bank>Protection Regions</bank>
     <description>Memory area 3 definition</description>
     <cpreg cp="15" crn="6" crm="3" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Region</display>
  </register>
  <register>
     <name>Region4</name>
     <bank>Protection Regions</bank>
     <description>Memory area 4 definition</description>
     <cpreg cp="15" crn="6" crm="4" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Region</display>
  </register>
  <register>
     <name>Region5</name>
     <bank>Protection Regions</bank>
     <description>Memory area 5 definition</description>
     <cpreg cp="15" crn="6" crm="5" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Region</display>
  </register>
  <register>
     <name>Region6</name>
     <bank>Protection Regions</bank>
     <description>Memory area 6 definition</description>
     <cpreg cp="15" crn="6" crm="6" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Region</display>
  </register>
  <register>
     <name>Region7</name>
     <bank>Protection Regions</bank>
     <description>Memory area 7 definition</description>
     <cpreg cp="15" crn="6" crm="7" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Region</display>
  </register>
  <register>
     <name>Invalidate</name>
         <bank>Cache operations</bank>
     <description>Invalidate cache</description>
     <cpreg cp="15" crn="7" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
</module>

<module>
  <type>ARM920T_CP15</type>
  <register>
     <name>ID</name>
     <description>Chip ID</description>
     <cpreg cp="15" crn="0" crm="0" opcode_2="0"></cpreg>
     <operation>dcache</operation>
     <access>RO</access>
     <width>32</width>
     <display>ChipID</display>
  </register>
  <register>
     <name>Type</name>
     <description>Cache type</description>
     <cpreg cp="15" crn="0" crm="0" opcode_2="1"></cpreg>
     <operation>icache</operation>
     <access>RO</access>
     <width>32</width>
     <display>CacheType</display>
  </register>
  <register>
     <name>Control</name>
     <description>Control</description>
     <cpreg cp="15" crn="1" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <display>CP15Control_920</display>
  </register>
  <register>
     <name>TTBR</name>
     <description>Translation table base register</description>
     <cpreg cp="15" crn="2" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <display>CP15TTBR</display>
  </register>
  <register>
     <name>DACR</name>
     <description>Domain access control register</description>
     <cpreg cp="15" crn="3" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <display>CP15DACR</display>
  </register>
  <register>
     <name>DFSR</name>
     <description>Fault status register</description>
     <cpreg cp="15" crn="5" crm="0" opcode_2="0"></cpreg>
     <operation>dcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15FSR</display>
  </register>
  <register>
     <name>PFSR</name>
     <description>Prefetch fault status register</description>
     <cpreg cp="15" crn="5" crm="0" opcode_2="1"></cpreg>
     <operation>icache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15FSR</display>
     <revision min="1"></revision>
  </register>
  <register>
     <name>FAR</name>
     <description>Fault address register</description>
     <cpreg cp="15" crn="6" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <display>CP15FAR</display>
  </register>
  <register>
     <name>DLOCK</name>
     <description>Data cache lockdown</description>
     <cpreg cp="15" crn="9" crm="0" opcode_2="0"></cpreg>
     <operation>dcache</operation>
     <access>RW</access>
     <width>32</width>
  </register>
  <register>
     <name>ILOCK</name>
     <description>Instruction cache lockdown</description>
     <cpreg cp="15" crn="9" crm="0" opcode_2="1"></cpreg>
     <operation>icache</operation>
     <access>RW</access>
     <width>32</width>
  </register>
  <register>
     <name>TLBDLOCK</name>
     <description>Data TLB lockdown</description>
     <cpreg cp="15" crn="10" crm="0" opcode_2="0"></cpreg>
     <operation>dcache</operation>
     <access>RW</access>
     <width>32</width>
  </register>
  <register>
     <name>TLBILOCK</name>
     <description>Instruction TLB lockdown</description>
     <cpreg cp="15" crn="10" crm="0" opcode_2="1"></cpreg>
     <operation>icache</operation>
     <access>RW</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate</name>
     <bank>Cache operations</bank>
     <description>Invalidate both caches</description>
     <cpreg cp="15" crn="7" crm="7" opcode_2="0"></cpreg>
     <operation>icache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate_I</name>
     <bank>Cache operations</bank>
     <description>Invalidate entire I cache</description>
     <cpreg cp="15" crn="7" crm="5" opcode_2="0"></cpreg>
     <operation>icache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate_I_Address</name>
     <bank>Cache operations</bank>
     <description>Invalidate I cache single entry (by address)</description>
     <cpreg cp="15" crn="7" crm="5" opcode_2="1"></cpreg>
     <operation>icache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Prefetch_I</name>
     <bank>Cache operations</bank>
     <description>Prefetch I cache line</description>
     <cpreg cp="15" crn="7" crm="13" opcode_2="1"></cpreg>
     <operation>icache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate_D</name>
     <bank>Cache operations</bank>
     <description>Invalidate entire D cache</description>
     <cpreg cp="15" crn="7" crm="6" opcode_2="0"></cpreg>
     <operation>dcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate_D_Address</name>
     <bank>Cache operations</bank>
     <description>Invalidate D cache single entry (by address)</description>
     <cpreg cp="15" crn="7" crm="6" opcode_2="1"></cpreg>
     <operation>dcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Clean_D_Address</name>
     <bank>Cache operations</bank>
     <description>Clean D cache single entry (by address)</description>
     <cpreg cp="15" crn="7" crm="10" opcode_2="1"></cpreg>
     <operation>dcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>CleanInvalidate_D_Address</name>
     <bank>Cache operations</bank>
     <description>Clean and invalidate D cache single entry (by address)</description>
     <cpreg cp="15" crn="7" crm="14" opcode_2="1"></cpreg>
     <operation>dcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Clean_D_Index</name>
     <bank>Cache operations</bank>
     <description>Clean D cache single index</description>
     <cpreg cp="15" crn="7" crm="10" opcode_2="2"></cpreg>
     <operation>dcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>CleanInvalidate_D_Index</name>
     <bank>Cache operations</bank>
     <description>Clean and invalidate D cache single index</description>
     <cpreg cp="15" crn="7" crm="14" opcode_2="2"></cpreg>
     <operation>dcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Drain</name>
     <bank>Cache operations</bank>
     <description>Drain write buffer</description>
     <cpreg cp="15" crn="7" crm="10" opcode_2="4"></cpreg>
     <operation>dcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Wait</name>
     <bank>Cache operations</bank>
     <description>Wait for interrupt</description>
     <cpreg cp="15" crn="7" crm="0" opcode_2="4"></cpreg>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate</name>
     <bank>TLB operations</bank>
     <description>Invalidate I+D TLB</description>
     <cpreg cp="15" crn="8" crm="7" opcode_2="0"></cpreg>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate_I</name>
     <bank>TLB operations</bank>
     <description>Invalidate I TLB</description>
     <cpreg cp="15" crn="8" crm="5" opcode_2="0"></cpreg>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate_I_Address</name>
     <bank>TLB operations</bank>
     <description>Invalidate I TLB entry (by address)</description>
     <cpreg cp="15" crn="8" crm="5" opcode_2="1"></cpreg>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate_D</name>
     <bank>TLB operations</bank>
     <description>Invalidate D TLB</description>
     <cpreg cp="15" crn="8" crm="6" opcode_2="0"></cpreg>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate_D_Address</name>
     <bank>TLB operations</bank>
     <description>Invalidate D TLB entry (by address)</description>
     <cpreg cp="15" crn="8" crm="6" opcode_2="1"></cpreg>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>PID</name>
     <description>Process ID register</description>
     <cpreg cp="15" crn="13" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <display>CP15PID</display>
  </register>
</module>

<module>
  <!-- The following data was obtained from reference [8]. -->
  <type>ARM922T_CP15</type>
  <register>
     <name>ID</name>
     <description>Chip ID</description>
     <cpreg cp="15" crn="0" crm="0" opcode_2="0"></cpreg>
     <operation>dcache</operation>
     <access>RO</access>
     <width>32</width>
     <display>ChipID</display>
  </register>
  <register>
     <name>Type</name>
     <description>Cache type</description>
     <cpreg cp="15" crn="0" crm="0" opcode_2="1"></cpreg>
     <operation>icache</operation>
     <access>RO</access>
     <width>32</width>
     <display>CacheType</display>
  </register>
  <register>
     <name>Control</name>
     <description>Control</description>
     <cpreg cp="15" crn="1" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <display>CP15Control_922</display>
  </register>
  <register>
     <name>TTBR</name>
     <description>Translation table base register</description>
     <cpreg cp="15" crn="2" crm="0" opcode_2="0"></cpreg>
     <access>RW</access