armperip.xml

These patch files are supplied as part of ADS 1.2.1.

     <width>32</width>
  </register>
</module>

<peripheral>
  <name>DCC_CP14</name>
  <component>
    <name>DCC</name>
    <type>DCC_CP14</type>
  </component>
</peripheral>

<!-- FPA and FPE -->

<module>
  <type>FPA</type>
  <register>
     <name>FPCR</name>
     <bank>FPA</bank>
     <cpreg cp="1" opcode_1="2" crn="0" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <dwarf>25</dwarf>
  </register>
  <register>
     <name>FPSR</name>
     <bank>FPA</bank>
     <cpreg cp="1" opcode_1="1" crn="0" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <dwarf>24</dwarf>
  </register>
  <register>
     <name>F0</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="8"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>16</dwarf>
  </register>
  <register>
     <name>F1</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="9"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>17</dwarf>
  </register>
  <register>
     <name>F2</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="10"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>18</dwarf>
  </register>
  <register>
     <name>F3</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="11"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>19</dwarf>
  </register>
  <register>
     <name>F4</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="12"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>20</dwarf>
  </register>
  <register>
     <name>F5</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="13"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>21</dwarf>
  </register>
  <register>
     <name>F6</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="14"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>22</dwarf>
  </register>
  <register>
     <name>F7</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="15"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>23</dwarf>
  </register>
</module>

<module>
  <type>FPE</type>
  <register>
     <name>FPSR</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="128"></memory>
     <access>RW</access>
     <width>32</width>
     <dwarf>24</dwarf>
  </register>
  <register>
     <name>F0</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="0" count="3"></memory>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>16</dwarf>
  </register>
  <register>
     <name>F1</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="0x10" count="3"></memory>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>17</dwarf>
  </register>
  <register>
     <name>F2</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="0x20" count="3"></memory>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>18</dwarf>
  </register>
  <register>
     <name>F3</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="0x30" count="3"></memory>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>19</dwarf>
  </register>
  <register>
     <name>F4</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="0x40" count="3"></memory>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>20</dwarf>
  </register>
  <register>
     <name>F5</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="0x50" count="3"></memory>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>21</dwarf>
  </register>
  <register>
     <name>F6</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="0x60" count="3"></memory>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>22</dwarf>
  </register>
  <register>
     <name>F7</name>
     <bank>FPE</bank>
     <memory base="$base" width="word" offset="0x70" count="3"></memory>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>23</dwarf>
  </register>
</module>

<peripheral>
  <name>FPE</name>
  <component>
    <name>FPE</name>
    <type>FPE</type>
  </component>
</peripheral>

<!-- Processors -->

<module>
  <type>ARM710T_CP15</type>
  <register>
     <name>ID</name>
     <description>Chip ID</description>
     <cpreg cp="15" crn="0" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RO</access>
     <width>32</width>
     <display>ChipID7</display>
  </register>
  <register>
     <name>Control</name>
     <description>Control</description>
     <cpreg cp="15" crn="1" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Control_710</display>
  </register>
  <register>
     <name>TTBR</name>
     <description>Translation table base register</description>
     <cpreg cp="15" crn="2" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15TTBR</display>
  </register>
  <register>
     <name>DACR</name>
     <description>Domain access control register</description>
     <cpreg cp="15" crn="3" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15DACR</display>
  </register>
  <register>
     <name>FSR</name>
     <description>Fault status register</description>
     <cpreg cp="15" crn="5" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15FSR</display>
  </register>
  <register>
     <name>FAR</name>
     <description>Fault address register</description>
     <cpreg cp="15" crn="6" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15FAR</display>
  </register>
  <register>
     <name>Invalidate</name>
         <bank>Cache operations</bank>
     <description>Invalidate cache</description>
     <cpreg cp="15" crn="7" crm="7" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate</name>
         <bank>TLB operations</bank>
     <description>Invalidate TLB</description>
     <cpreg cp="15" crn="8" crm="7" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
    <register>
     <name>Invalidate_Address</name>
         <bank>TLB operations</bank>
     <description>Invalidate TLB single entry (by address)</description>
     <cpreg cp="15" crn="8" crm="7" opcode_2="1"></cpreg>
     <operation>jointcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
</module>

<module>
  <type>ARM720T_CP15</type>
  <register>
     <name>ID</name>
     <description>Chip ID</description>
     <cpreg cp="15" crn="0" crm="0" opcode_2="0"></cpreg>
         <operation>jointcache</operation>
     <access>RO</access>
     <width>32</width>
     <display>ChipID7</display>
  </register>
  <register>
     <name>Control</name>
     <description>Control</description>
     <cpreg cp="15" crn="1" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Control_720</display>
  </register>
  <register>
     <name>TTBR</name>
     <description>Translation table base register</description>
     <cpreg cp="15" crn="2" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15TTBR</display>
  </register>
  <register>
     <name>DACR</name>
     <description>Domain access control register</description>
     <cpreg cp="15" crn="3" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15DACR</display>
  </register>
  <register>
     <name>FSR</name>
     <description>Fault status register</description>
     <cpreg cp="15" crn="5" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15FSR</display>
  </register>
  <register>
     <name>FAR</name>
     <description>Fault address register</description>
     <cpreg cp="15" crn="6" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15FAR</display>
  </register>
  <register>
     <name>Invalidate</name>
         <bank>Cache operations</bank>
     <description>Invalidate cache</description>
     <cpreg cp="15" crn="7" crm="7" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>Invalidate</name>
         <bank>TLB operations</bank>
     <description>Invalidate TLB</description>
     <cpreg cp="15" crn="8" crm="7" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
    <register>
     <name>Invalidate_Address</name>
         <bank>TLB operations</bank>
     <description>Invalidate TLB single entry (by address)</description>
     <cpreg cp="15" crn="8" crm="7" opcode_2="1"></cpreg>
     <operation>jointcache</operation>
     <access>WO</access>
     <width>32</width>
  </register>
  <register>
     <name>PID</name>
     <description>Process ID register</description>
     <cpreg cp="15" crn="13" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15PID</display>
  </register>
  <register>
     <name>Trace Process ID</name>
     <description>Trace Process ID</description>
     <cpreg cp="15" crn="13" crm="0" opcode_2="1"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <revision min="3"></revision>
  </register>
</module>

<module>
  <type>ARM740T_CP15</type>
  <register>
     <name>ID</name>
     <description>Chip ID</description>
     <cpreg cp="15" crn="0" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RO</access>
     <width>32</width>
     <display>ChipID7</display>
  </register>
  <register>
     <name>Control</name>
     <description>Control</description>
     <cpreg cp="15" crn="1" crm="0" opcode_2="0"></cpreg>
     <operation>jointcache</operation>
     <access>RW</access>
     <width>32</width>
     <display>CP15Control_740</display>
  </register>
  <register>
     <name>Cacheable</name>
     <description>Cacheable</description>