📄 translate_2.rpt
字号:
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 3/ 96( 3%) 0/ 48( 0%) 0/ 48( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\maxplus2\0110200330\translation\translate_2.rpt
translate_2
** EQUATIONS **
en : INPUT;
g0 : INPUT;
g1 : INPUT;
g2 : INPUT;
g3 : INPUT;
-- Node name is 'b0'
-- Equation name is 'b0', type is output
b0 = _LC4_A18;
-- Node name is 'b1'
-- Equation name is 'b1', type is output
b1 = _LC1_A19;
-- Node name is 'b2'
-- Equation name is 'b2', type is output
b2 = _LC3_A19;
-- Node name is 'b3'
-- Equation name is 'b3', type is output
b3 = _LC4_A21;
-- Node name is ':343'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = LCELL( _EQ001);
_EQ001 = g0 & g1 & g2 & !g3;
-- Node name is ':355'
-- Equation name is '_LC3_A18', type is buried
!_LC3_A18 = _LC3_A18~NOT;
_LC3_A18~NOT = LCELL( _EQ002);
_EQ002 = !g1
# g0
# g3
# !g2;
-- Node name is ':367'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ003);
_EQ003 = !g0 & g1 & !_LC2_A21;
-- Node name is ':379'
-- Equation name is '_LC3_A21', type is buried
!_LC3_A21 = _LC3_A21~NOT;
_LC3_A21~NOT = LCELL( _EQ004);
_EQ004 = !g1
# !g0
# _LC2_A21;
-- Node name is '~391~1'
-- Equation name is '~391~1', location is LC2_A21, type is buried.
-- synthesized logic cell
!_LC2_A21 = _LC2_A21~NOT;
_LC2_A21~NOT = LCELL( _EQ005);
_EQ005 = !g2 & !g3;
-- Node name is ':391'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ006);
_EQ006 = g0 & !g1 & !_LC2_A21;
-- Node name is ':435'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = LCELL( _EQ007);
_EQ007 = !g3
# !g2;
-- Node name is '~568~1'
-- Equation name is '~568~1', location is LC4_A19, type is buried.
-- synthesized logic cell
!_LC4_A19 = _LC4_A19~NOT;
_LC4_A19~NOT = LCELL( _EQ008);
_EQ008 = !g1 & g2 & !g3;
-- Node name is '~568~2'
-- Equation name is '~568~2', location is LC2_A19, type is buried.
-- synthesized logic cell
!_LC2_A19 = _LC2_A19~NOT;
_LC2_A19~NOT = LCELL( _EQ009);
_EQ009 = _LC3_A18
# _LC2_A18
# !_LC4_A19;
-- Node name is ':568'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = LCELL( _EQ010);
_EQ010 = _LC1_A18 & !_LC1_A21 & _LC2_A19 & !_LC3_A21;
-- Node name is '~574~1'
-- Equation name is '~574~1', location is LC7_A19, type is buried.
-- synthesized logic cell
_LC7_A19 = LCELL( _EQ011);
_EQ011 = !_LC1_A21 & !_LC3_A21;
-- Node name is ':574'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = LCELL( _EQ012);
_EQ012 = _LC1_A18 & !_LC2_A19 & _LC7_A19
# _LC1_A18 & _LC7_A19 & _LC8_A19;
-- Node name is '~580~1'
-- Equation name is '~580~1', location is LC6_A18, type is buried.
-- synthesized logic cell
_LC6_A18 = LCELL( _EQ013);
_EQ013 = en & g1
# en & g0
# en & _LC2_A21;
-- Node name is '~580~2'
-- Equation name is '~580~2', location is LC1_A18, type is buried.
-- synthesized logic cell
_LC1_A18 = LCELL( _EQ014);
_EQ014 = g1 & _LC6_A18
# !g0 & _LC6_A18
# _LC2_A21 & _LC6_A18;
-- Node name is '~580~3'
-- Equation name is '~580~3', location is LC5_A19, type is buried.
-- synthesized logic cell
_LC5_A19 = LCELL( _EQ015);
_EQ015 = !g3
# !g1 & !g2
# g1 & g2;
-- Node name is '~580~4'
-- Equation name is '~580~4', location is LC6_A19, type is buried.
-- synthesized logic cell
_LC6_A19 = LCELL( _EQ016);
_EQ016 = !_LC2_A18 & !_LC3_A18 & !_LC4_A19
# !_LC2_A18 & !_LC3_A18 & _LC5_A19;
-- Node name is ':580'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = LCELL( _EQ017);
_EQ017 = _LC1_A18 & _LC3_A21
# _LC1_A18 & _LC1_A21
# _LC1_A18 & _LC6_A19;
-- Node name is '~586~1'
-- Equation name is '~586~1', location is LC7_A18, type is buried.
-- synthesized logic cell
_LC7_A18 = LCELL( _EQ018);
_EQ018 = g0 & g1 & !g2
# !g0 & !g1 & !g2
# !g0 & g1 & g2
# g1 & !g3
# !g0 & !g3
# !g2 & !g3
# g0 & !g1 & g2 & g3;
-- Node name is '~586~2'
-- Equation name is '~586~2', location is LC8_A18, type is buried.
-- synthesized logic cell
_LC8_A18 = LCELL( _EQ019);
_EQ019 = _LC1_A21
# _LC2_A18 & !_LC3_A18
# !_LC3_A18 & _LC7_A18;
-- Node name is ':586'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = LCELL( _EQ020);
_EQ020 = _LC5_A18 & _LC6_A18
# !_LC3_A21 & _LC6_A18 & _LC8_A18;
Project Information d:\maxplus2\0110200330\translation\translate_2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,922K
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