config.lst

7302VideoAP.zip----------一个多媒体液晶显示器内部控制器(主芯片为:EL7302)的源程序(KC51)

C51 COMPILER V7.06   CONFIG                                                                11/29/2004 16:41:24 PAGE 1   


C51 COMPILER V7.06, COMPILATION OF MODULE CONFIG
OBJECT MODULE PLACED IN config.OBJ
COMPILER INVOKED BY: C:\KEIL\C51\BIN\C51.EXE config.c OPTIMIZE(0,SPEED) DEBUG OBJECTEXTEND

stmt level    source

   1          unsigned int  code PanelFactor[][8]={
   2          //Hsize , Vsize , Hwid , HBpor , HFpor , Vwid , VFpor , VBpor
   3           {1024  ,  768  ,  16  ,   32  ,  32   ,  10  ,  10   ,  10,  },//LG15
   4           {1280  , 1024  ,  16  ,   32  ,  32   ,  10  ,  10   ,  10,  },//CM17
   5           {1280  ,  768  ,  82  ,  200  , 180   ,  10  ,  15   ,  30,  },//WXGA
   6           {1280  , 1024  , 116  ,  132  , 132   ,  10  ,  10   ,  10,  },//AU17
   7           {1280  , 1024  ,  38  ,  248  , 112   ,  48  ,   3   ,  10,  },//SM17
   8          };
   9          /////////////////////////////////////////////////////////////////////////////////////////////////
  10          unsigned char code PanelControl[][17]={
  11          {//LG15
  12            1,    // PCLK0 invert("1"=invert)
  13            2,    // PCLK0 output phase delay(0~7)
  14            0,    // PCLK1 invert("1"=invert)
  15            0,    // PCLK1 output phase delay(0~7)
  16            0,    // Pixel output format(0/1:Single/Dual)
  17            0,    // Pixel Swap("0"=[23:0] are even/1st pixel)
  18            0,    // Hsync Polarity("0"=active low)
  19            0,    // Vsync Polarity("0"=active low)
  20            1,    // DE Polarity("0"=active low)
  21            8,    // Data bus driving strength
  22            8,    // Clock0 output driving strength
  23            8,    // Clock1 output driving strength
  24            0,    // (0/1:6-bit/8-bit panel)
  25            1,    // Dithering Enable
  26            0,    // Dual port parallel format enable
  27            0x08, // PLL Coarse Gain
  28            1     // Tcon function enable(1:not enable)
  29           },
  30          {//CM17
  31            0,    // PCLK0 invert("1"=invert)
  32            0,    // PCLK0 output phase delay(0~7)
  33            0,    // PCLK1 invert("1"=invert)
  34            0,    // PCLK1 output phase delay(0~7)
  35            1,    // Pixel output format(0/1:Single/Dual)
  36            //1,  // Pixel Swap("0"=[23:0] are even/1st pixel)//狾