📄 f51mble2.a51
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;************************************************************************
;* *
;* BOOTCODE (run-code) SUBROUTINES *
;* *
;************************************************************************
;************************************************************************
;
; Name: SECTOR ERASE ROUTINE (IAP CMD: 0Bh)
;
; ENTRY: (1) Starting Address (on a Sector Boundary)
; R4 = Address Byte High
; R5 = Address Byte Low
; (2) Sector Count (in R6)
;
; RETURNS: FLAGS
;
; DESTROYED: R0, R4, R5, R6
;
; This routine erases the sector(s) requested, beginning from the
; starting address provided. Notification is returned to the PC indicating
; success (FLAFS.2 = 0) or failure (FLAGS.2 = 1) of this operation.
;
;************************************************************************
sector_e:
mov a, r4 ; check if starting address in blk 0 or 1
anl a, #11110000b ; mask for upper 4 bits
cjne a, #0f0h, se_1 ; jump if blk 1 sector
mov r0, #SM_SIZE ; load small sector size for future use
sjmp se_st ; start sector erase
se_1:
mov r0, #LG_SIZE ; load large sector size for future use
se_st:
mov a, SFCF ; get SFCF
orl a, #MC0 ; set VIS & IAPEN bits = 1
mov SFCF, a ; ret. to SFCF, which enables 4K block & IAP
mov SFAH, r4 ; load high order address byte
mov SFAL, r5 ; load low order address byte
clr EA ; disable all interrupts before sector erase
mov SFCM, #SFCM_SE ; issue sector erase command
nop
nop
nop
acall done? ; wait for the sector erase operation
; to finish
setb EA ; enable all interrupts
jb err, se_e ; if timeout err detected, terminate
; the sector erase operation
djnz COUNT, se_nxt ; check if all sectors processed
se_e:
jnb TX, $
clr TX
mov a, FLAGS
mov SBUF, a ; send FLAGS byte to PC
nop
ret ; return to calling routine
se_nxt: ; configure for next sector
clr c
mov a, r5
add a, r0
mov r5, a ; low-byte address updated for next sector
mov a, r4
addc a, #00h
mov r4, a ; high-byte address updated for next sector
sjmp se_st ; go erase next sector
;************************************************************************
;
; Name: PROGRAM BYTE ROUTINE (IAP CMD: 0Eh)
;
; INPUTS: (1) Starting Address
; R4, DPH = AdrHi
; R5, DPL = AdrLo
; (2) Byte Count (in R6)
;
; RETURNS: (1) Send FLAGS to PC after each byte been programmed
; (2) Send FLAGS to PC after count of sector byte completed
;
; This routine receives the Starting Address and Length of Bytes to
; Write from the main loop. It then writes the data bytes received
; into the FlashFlex51 Block 0 flash memory program space. Notification
; is returned to the PC indicating success (FLAFS.2 = 0) or failure
; (FLAGS.2 = 1) of this operation.
;
;************************************************************************
program_b:
jnb RX, $ ; wait for command from PC
clr RX ; clear receive flag
mov a, B ; get command from B register
mov PCDATA, a ; get next data byte from PC
mov a, SFCF ; get SFCF
orl a, #MC0 ; set VIS & IAPEN bits = 1
mov SFCF, a ; ret. to SFCF, which enables 4K block & IAP
mov SFAH, DPH ; set address to write
mov SFAL, DPL
mov SFDT, PCDATA ; set data
mov SFCM, #SFCM_PB ; issue program-byte cmd
nop
nop
nop
acall done? ; wait for command to complete
jb ERR, pb_e ; stop processing if error occurs
inc DPTR ; point to next byte address to be written
mov a, FLAGS
jnb TX, $
clr TX
mov SBUF, a ; tell PC via the FLAGS byte
nop
djnz COUNT, program_b ; repeat loop until all data written
pb_1:
mov a, SFST
mov STATUS, a
jb FBUSY, pb_1 ; wait for last byte to be written
sjmp pb_2
pb_e:
mov a, FLAGS
jnb TX, $
clr TX
mov SBUF, a ; send error to PC
ret
pb_2:
mov a, FLAGS
jnb TX, $
clr TX
mov SBUF, a ; send status after last byte
nop
nop
ret ; return to calling routine
;************************************************************************
;
; Name: VERIFY BYTE ROUTINE (IAP CMD: 0Ch)
;
; INPUTS: (1) Starting Address
; R4, DPH = Address Byte High
; R5, DPL = Address Byte Low
; (2) Sector Byte Length (in R6)
;
; RETURNS: SFDT = Last Data Read
;
; DESTROYED: R4, R5, R6
;
; This routine reads the code bytes beginning at the flash memory location
; requested, and sends each data byte read immediately to the PC.
;
; Note: No error message is returned to PC if a timeout error because
; the PC knows the value to expect from the returned data, and it will
; perform its own processing on the data received.
;
;************************************************************************
verify_b:
mov a, SFCF ; get SFCF
orl a, #MC0 ; set VIS & IAPEN bits = 1
mov SFCF, a ; ret. to SFCF, which enables 4K block & IAP
mov SFAH, DPH ; load sfah with high address byte
mov SFAL, DPL ; load sfal with low address byte
mov SFCM, #SFCM_VB ; send verify byte command
nop
nop
nop
acall done? ; wait for command to complete
mov a, SFDT
jnb TX, $
clr TX
mov SBUF, a ; send data byte to PC
inc DPTR ; point to next data byte
djnz COUNT, verify_b ; next byte until count reaches zero
ret ; return to calling routine
;************************************************************************
;
; Name: BLOCK ERASE ROUTINE (IAP CMD: 0Dh)
;
; ENTRY: (1) Selecting lower block (block 0) Only
; R4 = Address Byte High
; R5 = Address Byte Low
; (2) Sector Count (in R6, not been used)
;
; RETURNS: FLAGS
;
; DESTROYED: R0, R4, R5, R6
;
; This routine erases block 0 Only. If a timeout condition is detected
; during erase operation, then the FLAGS byte will be forwarded to the PC
; as notification of the error condition.
;
;************************************************************************
block_e:
mov a, SFCF ; get SFCF
orl a, #MC0 ; set VIS & IAPEN bits = 1
mov SFCF, a ; ret. to SFCF, which enables 4K block & IAP
mov a, r4 ; check if starting address in blk 0
jz be_0 ; jump if blk 0 needs to be erased
sjmp be_er ; else jump to error routine
be_0:
mov SFAH, #00h
mov SFDT, #55h
clr EA ; disable all interrupts before sector erase
mov SFCM, #SFCM_BE ; issue block erase command
nop
nop
acall done? ; wait for the sector erase operation
; to finish
setb EA ; enable all interrupts
be_er: ; if timeout err detected, terminate
jnb TX, $ ; the sector erase operation
clr TX ; send FLAGS byte to PC no matter detect
mov a, FLAGS ; error or not
mov SBUF, a
nop
nop
ret ; return to calling routine
;************************************************************************
;
; Name: BURST PROGRAM ROUTINE (IAP CMD: 06h)
;
; INPUTS: (1) Starting Address
; R4, DPH = AdrHi
; R5, DPL = AdrLo
; (2) Byte Count in a row (one-half of a sector)
;
; RETURNS: FLAGS
;
; This routine receives the Starting Address and Length of Bytes to
; Write from the main loop. Each burst program can write a row or half
; of a sector. The status of FLAGS is sent to PC after burst.
;
;************************************************************************
burst_p:
mov a, SFCF ; get SFCF
orl a, #MC0 ; set VIS & IAPEN bits = 1
mov SFCF, a ; ret. to SFCF, which enables 4K block & IAP
mov SFAH, DPH ; set address to write
mov SFAL, DPL
bp_1:
jnb RX, $ ; wait for command from PC
clr RX ; clear receive flag
mov a, B ; get command from B register
mov PCDATA, a ; get next data byte from PC
mov SFDT, PCDATA ; set data
mov SFCM, #SFCM_BP ; issue burst-program cmd
acall done_byte? ; wait for byte program to complete
inc DPTR ; point to next byte address to be written
inc SFAL
djnz COUNT, bp_1 ; repeat loop until all data written
acall done? ; wait for the burst program operation
; to finish
mov a, FLAGS ; Tell PC via the FLAGS byte. The ERR bit
jnb TX, $ ; will be set if timeout error detected
clr TX
mov SBUF, a
nop
ret
;************************************************************************
; Poll BUSY/READY bit in SFST for every byte programmed *
;************************************************************************
done_byte?:
mov a, SFST ; put SFST into ACC
anl a, #00001000b ; AND or masked SFST[3]
cjne a, #Flash_Ready, done_byte? ; compare to 00h if not
; equal do again
ret
;************************************************************************
;
; Name: SET SECURITY BIT ROUTINE (PSEUDO IAP CMD: 04h)
;
; INPUTS: PCDATA hold the security bit selection
; 00h = security bit 1, execute IAP cmd 0Fh
; 01h = security bit 2, execute IAP cmd 03h
; 02h = security bit 3, execute IAP cmd 05h
;
; RETURNS: Nothing
;
; This routine will set the security bit selected to a logic 1.
;
; Note: No error message is returned to PC because the PC knows the lock
; states to expect after a successful chip-reset. However, the PC needs
; to insert a short time delay between two consecutive routines of
; set-security-bit. The "byte-program" time, T-PB, of SSTC54/58 MCU is equal
; to 110 micro-seconds; therefore, a delay time in PC for at least five
; milli-seconds is recommended.
;
;************************************************************************
security_lock:
mov SFDT, #55h ; issue IAP command setup
mov B, PCDATA ; load bit selection into B
mov A, #5 ; load A with multiplier
mul AB ; determine jump table offset
mov dptr, #scmd ; jump to designated security bit command
jmp @A+dptr ; based on table offset
scmd:
mov SFCM, #SFCM_SB1 ; set security bit 1
sjmp cmd_done
mov SFCM, #SFCM_SB2 ; set security bit 2
sjmp cmd_done
mov SFCM, #SFCM_SB3 ; set security bit 3
cmd_done:
mov a, SFST ; get status
anl a, #M4 ; mask for Flash Busy bit
cjne a, #Flash_Ready, cmd_done ; repeat loop until programming cmd done
nop
ret
;************************************************************************
;* *
;* CHECK WHETHER THE FLASH OPERATION IS COMPLETED *
;* *
;************************************************************************
;
; Maximum time in the done? subroutine = 0.42 seconds at a clock frequency
; of 11.0592 MHz. For frequencies other than 11.0592 MHZ, the equation
; for maximum time (in seconds) is 4.690992/f, where f = clock frequency
; in MHz.
;
done?:
mov r0, #255
loadr1: mov r1, #255
copy: mov a, SFST
mov STATUS, a
jnb FBUSY, ready ; polling SFST[2] for command completion
djnz r1, copy
djnz r0, loadr1
setb err ; indicates timeout error of the operation
ret
ready: clr err
ret
;************************************************************************
;* *
;* BOOTCODE SERIAL INTERRUPT SERVICE ROUTINE *
;* *
;************************************************************************
org 0F380H
bsl_rs232:
push ACC
jbc RI, rxdpc
clr TI
setb TX ; set flag for sent data to PC
pop ACC
reti
rxdpc: setb RX ; set flag for received data from PC
mov a, SBUF
mov B,a ; save in B register
clr TX ; clear transmit flag
mov SBUF,a ; resend to PC for comparison
pop ACC
reti
;=======================
ajmp loop ; software trap
nop
nop
nop
ajmp loop ; software trap
;************************************************************************
;* *
;* Instruction that changes the re-mapping should be in the portion of *
;* memory that is not affected by the re-mapping change. *
;* The current BSL code reqires 1 Kbyte of flash memory re-mapped. *
;* *
;************************************************************************
org 0F400h
usercode:
anl SFCF, #0FCh ; Deactivate memory re-mapping and long
ljmp USR_SECT0 ; jump to user reboot routine at 0000h
: of block 0
;=======================
END
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