setup_pfx_interrupts.asm

ADI BF DSP的CF卡的读写源码

/************************************************************************************************/
/*	The following routine first initializes PF4, PF5, PF6, and PF7 as inputs and enables        */
/*	interrupts on PF4, PF6, and PF7.  The following lists the MP3 playlist controls:			*/
/*  	1)  PF4:  Restart Current MP3 Song														*/
/*		2)  PF5:  Play / Vol Control																			*/
/*		3)  PF6:  Stop																			*/
/*		4)  PF7:  Go to Next MP3 Song															*/
/*															  Last Modified 03-10-03.  H. Desai */
/************************************************************************************************/

#include <def21535.h>

.GLOBAL Setup_PFx_Interrupts;

.SECTION program;

Setup_PFx_Interrupts:
P0.L = FIO_DIR & 0xFFFF;
P0.H = FIO_DIR >> 16;
R0 = W[P0];
R1.L = 0xFF0F;
R0 = R0 & R1;
W[P0] = R0;							//Set PF4 (RESTART CURRENT MP3 SONG), PF5 (PLAY / Vol Control), PF6 (STOP), and PF7 (NEXT MP3 SONG) as inputs

P0.L = FIO_MASKA_S & 0xFFFF;
P0.H = FIO_MASKA_S >> 16;
R0 = W[P0];
BITSET(R0,4);
BITSET(R0,5);
BITSET(R0,6);
BITSET(R0,7);
W[P0] = R0;							//Enable PF4, PF5, PF6, and PF7 interrupts

P0.H = FIO_EDGE >> 16;
P0.L = FIO_EDGE & 0xFFFF;
R0 = W[P0];
BITSET(R0,4);
BITSET(R0,5);
BITSET(R0,6);
BITSET(R0,7);
W[P0] = R0;							//Set edge sensitivity on PF4, PF5, PF6 and PF7

//Enable IVG12:  PF7 for 'Next MP3 Song' and PF6 for 'STOP' and PF5 for 'PLAY / Vol Control'
P0.H = (IMASK >> 16) & 0xFFFF;
P0.L = IMASK & 0xFFFF;
R2.L = W[P0];
R0.L = 0x1000;
R0 = R2 | R0;						//Clear IVG12 mask bit for PF4, PF5, PF6 and PF7 interrupts
W[P0] = R0.L;
CSYNC;
	
//Check revision of silicon 
P0.L = CHIPID & 0xffff;
P0.H = CHIPID >> 16;
R1 = [P0];
R2 = 0xF000(Z);
R1 = R1 & R2;
CC = BITTST(R1,28);  				// If the CHIPID is non-zero, a "1" in SIC_IMASK will enable system interrupts
IF CC JUMP NEW;

OLD:
//Unmask the PF Interrupt A in System Interrupt Mask Register
P0.L = SIC_IMASK & 0xffff;
P0.H = SIC_IMASK >> 16;
R1 = [P0];
BITCLR(R1,17);
[P0] = R1;

RTS;

NEW:
P0.L = SIC_IMASK & 0xffff;
P0.H = SIC_IMASK >> 16;
R1 = [P0];
BITSET(R1,17);   	// any rev of 1.0 or later will have system interrupts enabled by writing a 1 to the appropriate
[P0] = R1;     		// bit

RTS;