📄 ad1885_init.asm
字号:
P0.L = SPORT0_MRCS1 & 0xFFFF;
R1.L = 0x0000; /* ...disable the remaining channels */
W[P0] = R1.L; ssync;
P0.L = SPORT0_MRCS1 & 0xFFFF;
W[P0] = R1.L; ssync;
P0.L = SPORT0_MRCS2 & 0xFFFF;
W[P0] = R1.L; ssync;
P0.L = SPORT0_MRCS3 & 0xFFFF;
W[P0] = R1.L; ssync;
P0.L = SPORT0_MRCS4 & 0xFFFF;
W[P0] = R1.L; ssync;
P0.L = SPORT0_MRCS5 & 0xFFFF;
W[P0] = R1.L; ssync;
P0.L = SPORT0_MRCS6 & 0xFFFF;
W[P0] = R1.L; ssync;
P0.L = SPORT0_MRCS7 & 0xFFFF;
W[P0] = R1.L; ssync;
/* Set MCM Configuration Reg 1 - MCM enalbled , 1 frame delay, Win size = 16 Channels */
P0.L = SPORT0_MCMC1 & 0xFFFF;
R1.L = 0x0023;
W[P0] = R1.L; ssync;
/* Set MCM Configuration Reg 2 */
P0.L = SPORT0_MCMC2 & 0xFFFF;
R1.L = 0x000C;
W[P0] = R1.L; ssync;
/* SPORT0 Interrupts Unmasked */
//Check revision of silicon
P0.L = CHIPID & 0xffff;
P0.H = CHIPID >> 16;
R1 = [P0];
R2 = 0xf000(z);
R1 = R1 & R2;
cc = bittst(r1, 28); // If the CHIPID is non-zero, a "1" in SIC_IMASK will enable system interrupts
if cc jump new;
old:
//Unmask the PF Interrupt A in System Interrupt Mask Register
p0.l = SIC_IMASK & 0xffff;
p0.h = SIC_IMASK >> 16;
R1 = [p0];
BITCLR(R1,4);
[ P0 ] = R1;
RTS;
new:
p0.l = SIC_IMASK & 0xffff;
p0.h = SIC_IMASK >> 16;
R1 = [p0];
BITSET(R1,4); // any rev of 1.0 or later will have system interrupts enabled by writing a 1 to the appropriate
[ P0 ] = R1; // bit
RTS;
/************************************************************************************************/
/* DMA Controller Programming For SPORT0 */
/************************************************************************************************/
Program_DMA_Controller:
/* SPORT0 DMA AUTOBUFFER XMIT */
P0.L = SPORT0_CONFIG_DMA_TX & 0xFFFF; /* Set Autobuffer */
R3.L = 0x0010;
W[P0] = R3.L; ssync;
P0.L = SPORT0_START_ADDR_LO_TX & 0xFFFF;
p1.h = tx_buf;
p1.L = tx_buf; /* SPORT0 TX DMA Internal Memory Address */
r3 = p1;
W[P0] = r3.L; ssync;
P0.L = SPORT0_START_ADDR_HI_TX & 0xFFFF;
W[P0] = r3.H; ssync;
P0.L = SPORT0_COUNT_TX & 0xFFFF;
R3 = LENGTH(tx_buf); /* SPORT0 TX DMA Internal Memory Count */
W[P0] = R3; ssync;
/* SPORT0 DMA AUTOBUFFER RCV */
P0.L = SPORT0_CONFIG_DMA_RX & 0xFFFF; /* Set Autobuffer */
R3.L = 0x0010;
W[P0] = R3.L; ssync;
P0.L = SPORT0_START_ADDR_LO_RX & 0xFFFF;
p1.L = rx_buf; /* SPORT0 RX DMA Internal Memory Address */
p1.h = rx_buf;
r3 = p1;
W[P0] = r3.L; ssync;
P0.L = SPORT0_START_ADDR_HI_RX & 0xFFFF;
W[P0] = r3.H; ssync;
P0.L = SPORT0_COUNT_RX & 0xFFFF;
R3.L = LENGTH(rx_buf); /* SPORT0 RX DMA Internal Memory Count */
W[P0] = R3.L; ssync;
/* ENABLE SPORT0 DMA and DIRECTION IN DMA CONFIGURATION REGISTER */
P0.L = SPORT0_CONFIG_DMA_TX & 0xFFFF;
R3.L = 0x0011; /* Enable TX DMA */
W[P0] = R3.L; ssync;
P0.L = SPORT0_CONFIG_DMA_RX & 0xFFFF;
R3.L = 0x0017; /* Enable RX DMA, RX Direction (mem write), RX Interrupts */
W[P0] = R3.L; ssync;
RTS;
/************************************************************************************************/
/* AD1885 Codec Initialization */
/************************************************************************************************/
AD1885_Codec_Initialization:
P0.L = SPORT0_RX_CONFIG & 0xFFFF; /* Enable SPORT0 RX */
R3.L = W[P0];
BITSET (R3, 0);
W[P0] = R3.L; ssync;
P0.L = SPORT0_TX_CONFIG & 0xFFFF; /* Enable SPORT0 TX */
R3.L = W[P0];
BITSET (R3, 0);
W[P0] = R3.L; ssync;
STI R0; /* Enable Interrupts */
ssync; nop; nop;
idle; ssync; /* Wait for a few RX interrupts to ensure SPORT is up and running */
idle; ssync;
R3.L = 0x8000;
R2.h = 0x0000;
R2.l = 0x0000;
R3.h = 0x0000;
Wait_Codec_Ready:
idle; ssync;
P0.l = rx_buf;
p0.h = rx_buf;
R4.L = W[P0]; /* Get status bit 15 from AD1885 Tag - SLOT '0' */
R4.h = 0x0000;
R2 = R3 & R4;
CC = AZ;
if CC jump Wait_Codec_Ready;
R5.L = 0x020C; /* Assert PF 3 (LED 11 on 2191 EZKIT) indicating codec-DSP communication established */
P0.L = FIO_FLAG_S & 0xFFFF;
p0.h = (FIO_FLAG_S >> 16) & 0xFFFF;
W[P0] = R5.L;
/* Write Various registers of AD1885 to configre it - will read back these same registers to ensure they are properly configured */
Initialize_1885_Registers:
P0.l = Init_Codec_Registers;
P0.h = Init_Codec_Registers;
i3 = p0; /* Pointer to codec initialization commands */
l3 = 0;
P5 = 25;
R6.L = ENABLE_VFbit_SLOT1_SLOT2;
p0.h = tx_buf;
p0.l = tx_buf;
p0 += TAG_PHASE;
nop;
nop;
nop;
W[P0] = R6.L; /* Set 'Valid Slot' bits in TAG phase for SLOTS '0', '1' , '2' */
LOOP Codec_Init LC0 = P5;
LOOP_BEGIN Codec_Init;
P0.l = Init_Codec_Registers;
P0.h = Init_Codec_Registers;
nop;
nop;
nop;
R6.L = W[i3++]; /* Fetch next AD1885 register address */
p1.l = tx_buf;
p1.h = tx_buf;
p1 += COMMAND_ADDRESS_SLOT;
nop;
nop;
W[P1] = R6; /* ...put fetched codec register address into TX SLOT '1' */
R6.L = W[i3++]; /* Fetch register data contents */
p1 += -COMMAND_ADDRESS_SLOT;
p1 += COMMAND_DATA_SLOT;
nop;
nop;
nop;
W[P1] = R6; /* ...put fetched codec register data into TX SLOT '2' */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
idle; ssync;
idle; ssync; /* ...wait for 2 TDM frames... */
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
LOOP_END Codec_Init;
/* Verify AD1885 register writes */
verify_reg_writes:
p0.l = Init_Codec_Registers;
p0.h = Init_Codec_Registers;
i3 = p0;
l3 = 0;
p0.l = Codec_Init_Results;
p0.h = Codec_Init_Results;
i2 = p0;
l2 = 0;
P5 = 25;
R6.L = ENABLE_VFbit_SLOT1;
p0.l = tx_buf;
p0.h = tx_buf;
p0 += TAG_PHASE;
nop;
nop;
nop;
W[P0] = R6.L; /* Set 'Valid Slot' bits in TAG phase for SLOTS '0', '1' */
LOOP ad1885_register_status LC0 = P5;
LOOP_BEGIN ad1885_register_status;
R4.L = W[i3++]; /* Get next AD1885 register address that is to be read */
i3 += 2;
R3.L = 0x8000; /* Set bit #15 to signify AC'97 'Read-Request' in Command address word */
R4 = R4 | R3;
p1.l = tx_buf;
p1.h = tx_buf;
p1 += COMMAND_ADDRESS_SLOT;
nop;
nop;
nop;
W[P1] = R4.L; /* TX value out of Command address time slot */
idle; ssync; /* Wait for 5 AC'97 frames to go by, latency in getting data from AD1885 */
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
idle; ssync;
p0.l = rx_buf;
p0.h = rx_buf;
p0 += STATUS_ADDRESS_SLOT;
nop;
nop;
nop;
R4 = W[P0];
w[i2++] = R4.L;
p0 += -STATUS_ADDRESS_SLOT;
p0 += STATUS_DATA_SLOT;
R4 = W[P0];
w[i2++] = R4.L; /* Store to results buffer */
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
LOOP_END ad1885_register_status;
RTS; /* End of AD1885 Initialization */
/************************************************************************************************/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -