ad1885_init.asm

ADI BF DSP的CF卡的读写源码

/*****************************************************************************************************************

(C) Copyright 2001 - Analog Devices, Inc.  All rights reserved.

File Name:		AD1885_Init.asm

Date Modified:	02/26/03		H. Desai
				
Purpose:	   	AD1885/ADSP-21535 SPORT0 Initialization Driver 			
			   	Developed using the ADSP-BF535 EZ-Kit Lite Evaluation Platform		
				
				Demonstrate initialization and operation of a SPORT0-AC'97 link between the ADSPBF535 
			   	and sets up AD1885 to send/recieve data at 48 KHz using the SPORT0 rx ISR
				for audio processing.
				
*****************************************************************************************************************/	
#include 	<def21535.h>

/************************************************************************************************/
/*			   GLOBAL DECLARATIONS																*/	
/************************************************************************************************/ 


.GLOBAL 	Codec_Reset;			  
.GLOBAL		Program_SPORT0_Registers;
.GLOBAL		Program_DMA_Controller;
.GLOBAL		AD1885_Codec_Initialization;


 
/************************************************************************************************/
/*			     CONSTANT & MACRO DEFINITIONS													*/	
/************************************************************************************************/ 
/*			register				address	*/
/*         --------------		----------- */

#define		REGS_RESET				0x0000
#define		MASTER_VOLUME			0x0200
#define		HEAD_VOLUME				0x0400
#define		MASTER_VOLUME_MONO		0x0600	
#define		RESERVED_REG_2			0x0800
#define		PC_BEEP_Volume			0x0A00
#define		PHONE_Volume			0x0C00
#define		MIC_Volume				0x0E00
#define		LINE_IN_Volume			0x1000
#define		CD_Volume				0x1200
#define		VIDEO_Volume			0x1400
#define		AUX_Volume				0x1600
#define		PCM_OUT_Volume			0x1800
#define		RECORD_SELECT			0x1A00
#define		RECORD_GAIN				0x1C00
#define		RESERVED_REG_3			0x1E00
#define		GENERAL_PURPOSE			0x2000
#define		THREE_D_CONTROL_REG		0x2200
#define		RESERVED_REG_4			0x2400
#define		POWERDOWN_CTRL_STAT		0x2600
#define		EXTEND_AUDIO_ID			0x2800
#define		EXTEND_AUDIO_CTL		0x2A00
#define		SAMPLE_RATE_GENERATE_1	0x2C00
#define		SAMPLE_RATE_GENERATE_0	0x3200
#define 	JACK_SENSE				0x7200
#define		SERIAL_CONFIGURATION	0x7400
#define		MISC_CONTROL_BITS		0x7600
#define		VENDOR_ID_1				0x7C00
#define		VENDOR_ID_2				0x7E00

/* Mask bit selections in Serial Configuration Register for 
   accessing registers on any of the 3 codecs */
#define		MASTER_Reg_Mask			0x1000
#define		SLAVE1_Reg_Mask			0x2000
#define		SLAVE2_Reg_Mask			0x4000
#define		MASTER_SLAVE1			0x3000
#define		MASTER_SLAVE2			0x5000
#define		MASTER_SLAVE1_SLAVE2	0x7000

/* Macros for setting Bits 15, 14 and 13 in Slot 0 Tag Phase */
#define		ENABLE_VFbit_SLOT1_SLOT2	0xE000
#define		ENABLE_VFbit_SLOT1			0xC000
#define 	ENABLE_VFbit_STEREO			0x9800

/* TDM Timeslot Definitions */
#define		TAG_PHASE				0
#define		COMMAND_ADDRESS_SLOT	2
#define		COMMAND_DATA_SLOT		4
#define		STATUS_ADDRESS_SLOT		2
#define		STATUS_DATA_SLOT		4
#define		LEFT					6
#define		RIGHT					8

/*Uncomment the MIC macro if you are using MIC IN jumper settings on EZ-KIT*/
/*Leave the MIC macro commented if you are using LINE IN jumper settings on EZ-KIT (default setting)*/
//#define		MIC

/************************************************************************************************/
/* 				DM data 																		*/
/************************************************************************************************/
.SECTION program;
.align 2;
.byte2 	rx_buf[16]; 		/* receive buffer */
.GLOBAL rx_buf;
.align 2;							/* transmit buffer */ 
.byte2 	tx_buf[16] = 	ENABLE_VFbit_SLOT1_SLOT2, SERIAL_CONFIGURATION, 0x9900, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
						0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000;
.GLOBAL tx_buf;

#ifdef	MIC
.align 2;

/***********************************/
/* Codec Register Initializations */
/* - refer to AD1885 Data Sheet for register bit assignments */
//The following set of parameters is used for MIC IN jumper configuration on EZ-KIT
//Make sure the jumper configurations JP1 is set for MIC IN as this is not the default configuration
.byte2 Init_Codec_Registers[50] =       // these settings are for mic in
	REGS_RESET,				0xFFFF,
	MASTER_VOLUME,			0x0000,		/* Unmute Master Volume */
	HEAD_VOLUME,			0x0000,		/* Adjusted Headphone Vloume */
	MASTER_VOLUME_MONO,		0x8000,	
	PC_BEEP_Volume,			0x8000,
	PHONE_Volume,			0x8008,
	MIC_Volume,				0x8048,  //8008
	LINE_IN_Volume,			0x8808,
	CD_Volume,				0x8808,
	VIDEO_Volume,			0x8808,
	AUX_Volume,				0x8808,
	PCM_OUT_Volume,			0x0F0F,		/* Unmuted and attenuate by 10.5 dB */
	RECORD_SELECT,			0x0000,	//0404	/* Selected MIC IN as Record Select */
	RECORD_GAIN,			0x0a0a, //0000	/* Unmuted Record Gain */
	GENERAL_PURPOSE,		0x0000,		
	THREE_D_CONTROL_REG,	0x0000,
	POWERDOWN_CTRL_STAT,	0x0000,
	EXTEND_AUDIO_ID,		0x0001,
	EXTEND_AUDIO_CTL,		0x0001,
	SAMPLE_RATE_GENERATE_1,	0xBB80, //3b80		/*Sample Rate 14.875 KHz*/
	SAMPLE_RATE_GENERATE_0,	0xBB80, //3b80
	JACK_SENSE,				0x0000,
	MISC_CONTROL_BITS,		0x0404,
	VENDOR_ID_1,			0x4144,
	VENDOR_ID_2,			0x5360;
#else
//The following set of parameters is used for LINE IN jumper configuration on EZ-KIT (default)
.align 2;
.byte2 Init_Codec_Registers[50] =
	REGS_RESET,				0xFFFF,
	MASTER_VOLUME,			0x0000,		/* Unmute Master Volume */
	HEAD_VOLUME,			0x0F0F,		/* Adjusted Headphone Vloume */
	MASTER_VOLUME_MONO,		0x8000,	
	PC_BEEP_Volume,			0x8000,
	PHONE_Volume,			0x8008,
	MIC_Volume,				0x8008,
	LINE_IN_Volume,			0x8808,
	CD_Volume,				0x8808,
	VIDEO_Volume,			0x8808,
	AUX_Volume,				0x8808,
	PCM_OUT_Volume,			0x0F0F,		/* Unmuted and attenuate by 10.5 dB */
	RECORD_SELECT,			0x0404,		/* Selected LINE IN as Record Select */
	RECORD_GAIN,			0x0000,		/* Unmuted Record Gain */
	GENERAL_PURPOSE,		0x0000,		
	THREE_D_CONTROL_REG,	0x0000,
	POWERDOWN_CTRL_STAT,	0x0000,
	EXTEND_AUDIO_ID,		0x0001,
	EXTEND_AUDIO_CTL,		0x0001,
	SAMPLE_RATE_GENERATE_1,	44100,//0x3B80,		/*Sample Rate 14.875 KHz*/
	SAMPLE_RATE_GENERATE_0,	44100,//0x3B80,
	JACK_SENSE,				0x0000,
	MISC_CONTROL_BITS,		0x0404,
	VENDOR_ID_1,			0x4144,
	VENDOR_ID_2,			0x5360;
#endif
.align 2;
.byte2 Codec_Init_Results[50]; 	
.align 2;
.byte2 RX_Status = 0x8000;				/* RX Processing flag */
.GLOBAL RX_Status;



/************************************************************************************************/
/* AD1885 HARDWARE RESET																		*/
/* Toggle flag_15 to assert and deassert 1885_RESET											 	*/
/************************************************************************************************/

Codec_Reset:


	P0.L = FIO_DIR & 0xFFFF;
	P0.H = (FIO_DIR >> 16) & 0xFFFF;
	R0.L = W[P0];
	BITSET(R0,15);					/* Configure PF I/O pin 15 as output */
	BITSET(R0,3);
	BITSET(R0,2);
	BITSET(R0,1);
	BITSET(R0,0);
	W[P0] = R0.L; ssync;

	P1.L = FIO_FLAG_S & 0xFFFF;				/* Initialize Output PFx Pins OFF */
	P1.H = (FIO_FLAG_S >> 16) & 0xFFFF;
	R0.L = 0x800C;
	W[P1] = R0.L; ssync;

	P5.L = 0x0000;		/* So we can see the lights blink */
	P5.H = 0x1000;
	LOOP blink_LEDs LC0 = P5;	/* Duration of 1 usec */
	LOOP_BEGIN blink_LEDs;
	nop;
	LOOP_END blink_LEDs;

	P1.L = FIO_FLAG_C & 0xFFFF;				/* Assert AD1885 /RESET (active low) */
	P1.H = (FIO_FLAG_C >> 16) & 0xFFFF;
	R0.L = 0x800B;
	W[P1] = R0.L; ssync;

	P5 = 0x00000140;		    /* AD1885 /Reset Active low for 1 usec assuming 160Mhz DSP Core CLK */
	LOOP hold_reset LC0 = P5;	/* Duration of 1 usec */
	LOOP_BEGIN hold_reset;
	nop;
	LOOP_END hold_reset;

	P2.L = FIO_FLAG_S & 0xFFFF;
	P2.H = (FIO_FLAG_S >> 16) & 0xFFFF;
	R0.L = 0x8004;				/* De-assert AD1885 /RESET and turn-on PF_2 (LED_10)*/
	W[P2] = R0.L; ssync;
		
	P5.L = 0xD480;	/* 170 usec to allow the Codec to recover from Reset */
	P5.H = 0x3F00;
	LOOP reset_recovery_delay LC0 = P5;
	LOOP_BEGIN reset_recovery_delay;
	nop;
	LOOP_END reset_recovery_delay;


	RTS;
	
/************************************************************************************************/
/* SPORT0 CONTROL REGISTER PROGRAMMING															*/


Program_SPORT0_Registers:
	P0.H = (IMASK >> 16) & 0xFFFF;
	P0.L = IMASK & 0xFFFF;
	R2.L = W[P0];
	R0.L = 0x0100;
	R0 = R2 | R0;						/* Clear SPORT0 RX mask bit */
	W[P0] = R0.L;
	csync;
	CLI R0;								/* Disable all interrupts */
	R1.L = 0x0000;
	[P0] = R1;								/* Initially no interrupts */

/* RESET SPORT0 & DMA */
	P0.H = (SPORT0_TX_CONFIG >> 16) & 0xFFFF;
	P0.L = SPORT0_TX_CONFIG & 0xFFFF;
	R1.L = 0x0000;
	W[P0] = R1.L; ssync;
  	P0.L = SPORT0_RX_CONFIG &0xFFFF;
	W[P0] = R1.L; ssync;
  	P0.L = SPORT0_MCMC1 & 0xFFFF;
	W[P0] = R1.L; ssync;				
	
	P0.L = SPORT0_IRQSTAT_RX & 0xFFFF;
	R1.L = 0x0003;
	W[P0] = R1.L; ssync;
	P0.L = SPORT0_IRQSTAT_TX & 0xFFFF;
	W[P0] = R1.L;  ssync;

/* Set SPORT0 frame sync divisor */
  	P0.L = SPORT0_RFSDIV & 0xFFFF;			/* AC'97 48Khz Frame Sync with 12.288Mhz Input Clock */
	R1.L = 0x00FF;
	W[P0] = R1.L; ssync;

/* Set SPORT0 frame sync divisor */
  	P0.L = SPORT0_TFSDIV & 0xFFFF;			/* AC'97 48Khz Frame Sync with 12.288Mhz Input Clock */
	R1.L = 0x00FF;
	W[P0] = R1.L; ssync;


	P0.L = SPORT0_RSCLKDIV & 0xFFFF;			/* AC'97 48Khz Frame Sync with 12.288Mhz Input Clock */
	R1.L = 0x0005;
	W[P0] = R1.L; ssync;

/* Set: Internal RFS, 16-bits receive, External clock */
  	P0.L = SPORT0_RX_CONFIG & 0xFFFF;
	R1 = 0x03E0;
	W[P0] = R1; ssync;

/* Set: 16-bits transmit */
  	P0.L = SPORT0_TX_CONFIG & 0xFFFF;
	R1 = 0x01E0;
	W[P0] = R1; ssync;

/* Enable MCM Transmit and Receive Channels */
  	P0.L = SPORT0_MTCS0 & 0xFFFF;							/* Enable 16 Channels for TX */
	R1.L = 0xFFFF;
	W[P0] = R1.L; ssync;

	P0.L = SPORT0_MTCS1 & 0xFFFF;
	R1.L = 0x0000;							/* ...disable the remaining channels */								
  	W[P0] = R1.L; ssync;

	P0.L = SPORT0_MTCS1 & 0xFFFF;
  	W[P0] = R1.L; ssync;

	P0.L = SPORT0_MTCS2 & 0xFFFF;
  	W[P0] = R1.L; ssync;

	P0.L = SPORT0_MTCS3 & 0xFFFF;
  	W[P0] = R1.L; ssync;

	P0.L = SPORT0_MTCS4 & 0xFFFF;
  	W[P0] = R1.L; ssync;

	P0.L = SPORT0_MTCS5 & 0xFFFF;
  	W[P0] = R1.L; ssync;

	P0.L = SPORT0_MTCS6 & 0xFFFF;
  	W[P0] = R1.L; ssync;

	P0.L = SPORT0_MTCS7 & 0xFFFF;
  	W[P0] = R1.L; ssync;

  	P0.L = SPORT0_MRCS0 & 0xFFFF;							/* Enable 16 Channels for RX */
	R1.L = 0xFFFF;
	W[P0] = R1.L; ssync;