read_cf.asm

ADI BF DSP的CF卡的读写源码

/************************************************************************************************/
/*	The following routines do:																	*/
/*		1)	Compact Flash software reset														*/
/*		2)	CF sector read																		*/
/*		3)	extract drive information from CF													*/
/*		4)	read MP3s off of CF and place data in little endian format in pack_buffer			*/
/*						Last Modified 02-26-03.  												*/
/*						  		      04-24-03:  Removed unnecessary CLI and STI instructions. 	*/
/*												 Put in benchmark code (commented out)			*/
/*																					   H. Desai	*/
/************************************************************************************************/					

#define Mem_Mapped_Registers 0x24000800

.GLOBAL CF_Soft_Reset;
.GLOBAL Read_Sector_CF;
.GLOBAL Identify_Drive_Command;
.GLOBAL Read_MP3;

.EXTERN Check_CF_Busy;
.EXTERN Check_CF_RDY_Status;
.EXTERN Check_CF_ERR_Status;
.EXTERN Check_CF_DRQ_Status;
.EXTERN Save_IMASK;
.EXTERN Single_Sector_Benchmark;

.SECTION program;

/******************************************/
CF_Soft_Reset:
	P0.H = 0x2400;
	P0.L = 0x0200;					//Configuration Option Register, Attribute Memory (A11 = 1)
		
	R0 = 0x80;
	B[P0] = R0;						//Set SRESET bit in Configuration Option Register

	nop;
	nop;
	nop;
	R0 = B[P0];
	
	P5.H = 0x0000;
	P5.L = 0x1D4C;					//Assert CF RESET for minimum recommended RESET width time
	LSETUP(DELAY_BEGIN, DELAY_END) LC0 = P5;//Duration of 25 usec
	DELAY_BEGIN:
	DELAY_END:	NOP;

	R0 = 0x0000;
	W[P0] = R0;						//De-assert CF RESET

	RTS;

/******************************************/
Read_Sector_CF:

/**Initialize Benchmarking**/
//R0 = 0x0 (Z);
//CYCLES = R0;
//CYCLES2 = R0;
//R0 = SYSCFG;
//BITSET(R0,1);
//SYSCFG = R0;
/**Start Benchmarking Read Single Sector Code Here**/

	R4 = RETS;
	CALL Check_CF_Busy;
	
	P0.H = Mem_Mapped_Registers >> 16;
	P0.L = Mem_Mapped_Registers & 0xFFFF;

	I2.H = Save_IMASK;
	I2.L = Save_IMASK;
		
	W[P0+0x2] = R1;					//Write to ATA Sector Count & Sector No. Registers
	CALL Check_CF_RDY_Status;
	W[P0+0x4] = R2;					//Write to ATA Cylinder Low & Cylinder High Registers
	CALL Check_CF_RDY_Status;
	W[P0+0x6] = R3;					//Write to ATA Drive/Head & Command Registers 				
	CALL Check_CF_RDY_Status; 		//Check CF ATA Status Register RDY bit set
	CALL Check_CF_ERR_Status;		//Check CF ATA Status Register ERR bit set
	CALL Check_CF_DRQ_Status; 		//Check CF ATA Status Register Data Request bit set
	
	CALL Check_CF_Busy;

	CLI R0;
	[I2] = R0;
	
	P5.H = 0x0000;
	P5.L = 0x0100;				
	LSETUP(Read_Data_BEGIN, Read_Data_END) LC1 = P5;
	Read_Data_BEGIN:	R0 = W[P0+0x8];
	Read_Data_END:		W[I0++] = R0.L;
	
	R0 = [I2];
	STI R0;
	
/**Disable Benchmarking and Read Cycles Count**/
//R0 = SYSCFG;
//BITCLR(R0,1);
//SYSCFG = R0;	//Stop Benchmarking Here
//R0 = CYCLES;
//R1 = CYCLES2;
//P0.H = Single_Sector_Benchmark;
//P0.L = Single_Sector_Benchmark;
//[P0] = R0;
//[P0+4] = R1;

	RETS = R4;
	RTS;

/******************************************/
Identify_Drive_Command:
	R4 = RETS;
	CALL Check_CF_Busy;
	CALL Check_CF_RDY_Status;

	R3.L = 0xECA0;					//Issue Identify Drive Command
	W[P0+0x6] = R3;					//Write to ATA Drive/Head & Command Registers 				
	CALL Check_CF_RDY_Status; 		//Check CF ATA Status Register RDY bit set
	CALL Check_CF_DRQ_Status; 		//Check CF ATA Status Register Data Request bit set
	
	CALL Check_CF_Busy;
	
	P5.H = 0x0000;
	P5.L = 0x0100;				
	LSETUP(IRead_Data_BEGIN, IRead_Data_END) LC0 = P5;
	IRead_Data_BEGIN:	R0 = W[P0+0x8];
	IRead_Data_END:		W[I0++] = R0.L;

	RETS = R4;
	RTS;												
	
/******************************************/
Read_MP3:
	R4 = RETS;
	CALL Check_CF_Busy;

	P0.H = Mem_Mapped_Registers >> 16;
	P0.L = Mem_Mapped_Registers & 0xFFFF;
	
	I2.H = Save_IMASK;
	I2.L = Save_IMASK;
		
	W[P0+0x2] = R1;					//Write to ATA Sector Count & Sector No. Registers
	CALL Check_CF_RDY_Status;
	W[P0+0x4] = R2;					//Write to ATA Cylinder Low & Cylinder High Registers
	CALL Check_CF_RDY_Status;
	W[P0+0x6] = R3;					//Write to ATA Drive/Head & Command Registers 				
	CALL Check_CF_RDY_Status; 		//Check CF ATA Status Register RDY bit set
	CALL Check_CF_ERR_Status;		//Check CF ATA Status Register ERR bit set
	CALL Check_CF_DRQ_Status; 		//Check CF ATA Status Register Data Request bit set
	
	CALL Check_CF_Busy;

	CLI R0;
	[I2] = R0;
	
	P5.H = 0x0000;
	P5.L = 0x0080;				
	LSETUP(Read_MP3_BEGIN, Read_MP3_END) LC1 = P5;
	Read_MP3_BEGIN:	R0 = [I2];
					STI R0;
					NOP; NOP; NOP;
					CLI R0;
					[I2] = R0;

					R0 = W[P0+0x8];	//read word from CF
					R1.L = R0.L << 8;
					R0 = R0 >> 8;
					R1 = R0 | R1;
					R1 <<= 16;
					R0 = W[P0+0x8];	//read word from CF
					R2.L = R0.L << 8;
					R0 = R0 >> 8;
					R2 = R0 | R2;
					R0 = R1 | R2;
	Read_MP3_END:	[I0++] = R0;	//and place in little endian format into pack_buffer

	R0 = [I2];
	STI R0;
	
	RETS = R4;
	RTS;

/******************************************/