spihost.asm

ADI SHARC DSP系统启动源码

/* ------------------------ SPIhost.asm ---------------------------------------
	Version 1.0 24.Feb.02 - B. Mitchell

	This project is intended for a single ADSP-21161 processor.

	This code is to be used to boot a slave ADSP-21161 while including a form
	of SPI feedback as described in EE-177. Prior to any user modifications,
	FLAG0 on the host DSP should be connected to the SPIDS pin on the slave,
	and FLAG4 should be connected to FLAG0 on the slave DSP.
	
	The boot data to be sent to the slave is contained in spiloader.ldr.
------------------------------------------------------------------------------*/

#include <def21161.h>
#define OFFSET 2 // Depth of FIFO on SPI buffer (# of words to resend)


/* Data section to host the loader file */
.section/dm	seg_dmda;
.var master_tx_buf[] = "spiloader.ldr"; //kernel in 32-bit include format

/* Main code section */
.section/pm	seg_pmco;
_main:
		r0=0x00000000;			// initially clear SPI control register
		dm(SPICTL)=r0;

		// Send the first 256 words (kernel) for the initial boot of the slave
	    r0=master_tx_buf;		//configure index register for SPI transmit
		dm(IISTX)=r0;

		r0=0x180;		//configure count register for SPI transmit
		dm(CSTX)=r0;

		r0=1;				//configure modify register for SPI transmit
		dm(IMSTX)=r0;

		ustat1=0;
		bit set ustat1  MS | WL32 | BAUDR1 | SPTINT | SPIEN | TDMAEN | FLS0 | PSSE;
        dm(SPICTL) = ustat1;		// start transfer by configuring SPICTL

/* Wait for the kernel to finish transferring */
		lcntr=3, do later until lce;
wait:   lcntr=0xffffff;	  do (pc,1) until LCE;
		nop;
later:	nop;

		r0=0x00000000;			// clear SPI control register before reinitializing
		dm(SPICTL)=r0;

		// No need to reconfigure the IISTX register, DMA will continue where it left off.

		r0= @master_tx_buf - 0x180;		// configure count register for SPI transmit
		dm(CSTX)=r0;

		r0=1;				// configure modify register for SPI transmit
		dm(IMSTX)=r0;

		ustat1=0;
		bit set ustat1  MS | WL32 | BAUDR1 | SPTINT | SPIEN | TDMAEN | FLS0 | PSSE;
        dm(SPICTL) = ustat1;		// start transfer by configuring SPICTL

// Watch for FLAG4 to go low indicating that the slave has entered a zero init section.
waiting_for_pause:
		ustat1=dm(IOFLAG);
		bit tst ustat1 FLG4;
		if not tf jump stop_spi;
waiting_for_pause.end:		jump waiting_for_pause;
_main.end:

// End of code, stay here forever.
waiter:	nop;
        jump waiter;
waiter.end:

// Pause SPI transmission until the slave is ready.
stop_spi:
		bit clr lirptl SPITI; // Clear any pending SPITX interrupt
		r1=dm(CSTX);	// Save count register
		r2=dm(IISTX);	// Save index register

		r3=1;
		dm(CSTX)=r3;	// Set DMA count register to 1 to stop DMA

		bit set lirptl SPITMSK;
		bit set imask LPISUMI;
		bit set mode1 IRPTEN;	// Unmask SPITX interrupt.

		// Update the count and index registers to reflect the two words that will be lost.
		r4=OFFSET;r1=r1+r4;r2=r2-r4;nop;
		idle;	// Wait for the SPI transmission to finish

		r0 = 0;			//Disable the SPI
		dm(SPICTL) = r0;
		r10=0;

		ustat1=dm(IOFLAG);	//Monitor FLAG4 to know when the slave is ready
		r10=r10+1;	// Count how long the slave is holding off transmission.
		bit tst ustat1 FLG4;
		if not tf jump (pc,-3);

		dm(CSTX)=r1;	// Reload the DMA control registers with corrected values.
		dm(IISTX)=r2;

		ustat1 = dm(SPICTL);	//Reenable SPI Transmission
		bit set ustat1  MS | WL32 | BAUDR1 | SPTINT | SPIEN | TDMAEN | FLS0 | PSSE;
		dm(SPICTL) = ustat1;

		jump waiter;
stop_spi.end:



.section/pm seg_rth;
// Run-time header, code starts here.
                nop;nop;nop;nop;
Chip_Reset:     idle; jump _main; nop; nop;

.global spi_tx_isr;
//SPI interrupt vector, automatically placed in correct position in LDF file
spi_tx_isr:     r15=0xfffff;
                rti;
spi_tx_isr.end: