📄 erosion.asm
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/*******************************************************************************
Copyright(c) 2000 - 2002 Analog Devices. All Rights Reserved.
Developed by Joint Development Software Application Team, IPDC, Bangalore, India
for Blackfin DSPs ( Micro Signal Architecture 1.0 specification).
By using this module you agree to the terms of the Analog Devices License
Agreement for DSP Software.
********************************************************************************
Module name : erosion.asm
Label name : __erosion
Version : 1.1
Change History :
Version Date Author Comments
1.1 01/28/2002 Raghavendra Modified to match
silicon cycle count
1.0 06/29/2001 Raghavendra Original
Description : This function performs erosion on the input binary image.
The structured elements are stored as below
| h00 h01 h02 |
| h10 h11 h12 |
| h20 h21 h22 |
If input under consideration is
| x00 x01 x02 |
| x10 x11 x12 |
| x20 x21 x22 |
Then out put Y11 == ((x00&h00) &(x01&h01) & (x02&h02)
&(x10&h10) &(x11&h121) & (x12&h12)
& (x20 &h20) &(x21&h21) &(x22 &h22))
The values in first row,last row ,first column and last column
output are treated as zero.
Assumption : 1. Number of columns of input image is even AND aligned to
word boundary
2. Input image and structured elements should be in different
Banks
Prototype : void _erosion(unsigned char* in, int row, int col,
short * mask, unsigned char *out );
in -> It is pointer to the input image.
row -> It is number of rows of input image.
col -> It is number of columns of input image.
mask -> It is pointer 3x3 mask.
out -> It is pointer the output buffer.
Registers used : A0, A1, R0-R7, I1, B1, L1, P0-P5, LC0, LC1.
Performance:
Code size : 232 bytes
Cycle count : 474 Cycles for 8x8 image
Inner loop : 10.5* (column-2)
Outer loop : 5* (Row-2)
first row and last row : 2*column
*******************************************************************************/
.section L1_code;
.global __erosion;
.align 8;
__erosion:
[--SP]=(R7:4,P5:3);
R5=R1-R1(NS) ||R7=[SP+40];
// Address of structured element and clear R5
I1=R7; // Initialize I register to structure element
// address
B1=R7; // Initialize base register
L1=18; // Initialize L register
P5=R0; // Address of input array
P1=R2; // Number of columns
P3=R2; // Number of columns
P2=R1; // Number of rows
R6=R1-R1(NS)||P4=[SP+44]|| R1.L=W[I1++];
// Address of output array and fetch h00
P0=9; // set loop counter to 9
LSETUP(CORE_THRESH,CORE_THRESH)LC0=P0;
CORE_THRESH:
R6=R6+R1(NS) || R1.L=W[I1++];
// Accumulate structured elements to get threshold
NOP;
P0=R2; // Number of columns (N)
//////////////////// First Row ///////////////////////////////////////////////
LSETUP(FIRST_ROW_ST,FIRST_ROW_ST)LC0=P1;
FIRST_ROW_ST:
B[P4++]=R5;
// Clear first row
R3=R2<<1 ||R0=B[P5++](Z);
// R3= 2*Col,fetch first input
P0+=-4; // Columns -4
R3+=2;
P1+=-2; // Col-2
P2+=-2; // ROW-2;
R7=1;
///////////// Middle Rows ///////////////////////////////////////////////
//
LSETUP(ROW_ST,ROW_END)LC0=P2;
// loop counter == ROW-2 (M-2)
P2=R3; // 2*col +2
ROW_ST:
B[P4++]=R5;
LSETUP(COL_ST,COL_END)LC1=P1>>1;
// loop counter ==(COL-2)/2
COL_ST: A0=R0.L*R1.L(IS) ||R0=B[P5++](z) || R1.H=W[I1++];
// fetch x(0,1) and h01
A1=R0.L * R1.L ,A0+=R0.L*R1.H(IS) || R0=B[P5++](z) || R1.L=W[I1++];
// fetch x(1,2) and h02
A1+=R0.L *R1.H ,A0+=R0.L *R1.L(IS) || R0=B[P5++](z) ||R1.H=W[I1++];
// fetch x(1,3) and h10
R4=R1-R1(NS)||R3=W[P5++P0](Z);
// move P5 to starting of next row
A1+= R0.L *R1.L (IS) ||R0=B[P5++](z) ||R1.L=W[I1++];
// fetch x(1,0) and h11
A0+=R0.L *R1.H(IS)|| R0=B[P5++](z) ;
// fetch x(1,1)
A1+=R0.L * R1.H,A0+=R0.L *R1.L(IS) ||R0=B[P5++](z)|| R1.H=W[I1++];
// fetch x(1,2) and h12
A1+= R0.L *R1.L ,A0+=R0.L *R1.H(IS)|| R0=B[P5++](z)||R1.L=W[I1++];
// fetch x(1,3) and h20
R2=W[P5++P0](Z); // move P5 to starting of next row
A1+= R0.L *R1.H(IS)||R0=B[P5++](z)|| R1.H=W[I1++];
// fetch x(2,0) and h21
A0+=R0.L*R1.L(IS) ||R0=B[P5++](z);
// fetch x(2,1)
A1+=R0.L * R1.L ,A0+=R0.L *R1.H(IS) ||R0=B[P5++] (z)||R1.L=W[I1++];
// fetch x(2,2) and h22
A1+=R0.L *R1.H,R2=(A0+=R0.L *R1.L)(IS)||R0=B[P5++](z);
// fetch x(2,3)
CC=R2==R6; // compare r2 with threshold
IF CC R4=R7; // if true r4==1
R2=R1-R1(NS)||B[P4++]=R4;
// store first output
P5-=P2; // modify P5 to process next set of data
R3=(A1+=R0.L *R1.L)(IS)||R0=B[P5++] (z)|| R1.L=W[I1++];
// fetch x(0,2) and h00
CC=R3==R6; // compare r3 with threshold
IF CC R2=R7; // if true r2==1
COL_END: B[P4++]=R2;
// store next output
P5+=1; // Increment P5 to starting of next row
R0=B[P5++](Z) ; // fetch first element
ROW_END:B[P4++]=R5;
// store last element as zero
////////////////////// LAST ROW /////////////////////////////////////////
LSETUP(LAST_ROW_ST,LAST_ROW_ST)LC0=P3;
LAST_ROW_ST:
B[P4++]=R5 ;
// store last row as zero
(R7:4,P5:3)=[SP++]; // POP r7 and P5-3
RTS;
NOP; // To avoid one stall if LINK or UNLINK happens to
// be the next instruction in the memory.
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