📄 dilation.asm
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/*******************************************************************************
Copyright(c) 2000 - 2002 Analog Devices. All Rights Reserved.
Developed by Joint Development Software Application Team, IPDC, Bangalore, India
for Blackfin DSPs ( Micro Signal Architecture 1.0 specification).
By using this module you agree to the terms of the Analog Devices License
Agreement for DSP Software.
********************************************************************************
Module Name : dilation.asm
Label name : __dilation
Version : 1.1
Change History :
Version Date Author Comments
1.1 01/28/2002 Raghavendra Modified to match
silicon cycle count
1.0 06/29/2001 Raghavendra Original
Description : This function performs dilation on the binary input image.
The structured elements are stored as below
| h00 h01 h02 |
| h10 h11 h12 |
| h20 h21 h22 |
If input under consideration is
| x00 x01 x02 |
| x10 x11 x12 |
| x20 x21 x22 |
Then out put
Y11 == ((x00&h00) |(x01&h01) | (x02&h02) |(x10&h10) |(x11&h121)
| (x12&h12)| (x20 &h20)|(x21&h21) |(x22 &h22))
Prototype : void _dilation(unsigned char* in, int row, int col,
short * mask, unsigned char *out );
in -> It is pointer to the input image.
row -> It is number of rows of input image.
col -> It is number of columns of input image.
mask -> It is pointer 3x3 mask.
out -> It is pointer the output buffer.
Assumption : 1. Number of columns in input image is even AND aligned to
word or half word boundary
2. Input image and structured elements are in different Banks
Registers used : A0, A1, R0-R3, R6-R7, I1, B1, M0-M3, L1, P0-P5, LC0, LC1.
Performance :
Code size : 722 bytes
Cycle count : 760 cycles for 8x8 image
First and Last Row : 12* (Column-2)
Four corner elements : 38 cycles.
Middle rows :
Inner loop :10.5*(column-2)
Outer loop : 26*(Row-2)
*******************************************************************************/
.section L1_code;
.global __dilation;
.align 8;
__dilation:
[--SP] = (R7:6,P5:3);
R7 = [SP+32]; // Address of structured element
I1 = R7; // Initialize I register to structure element
// address
B1 = R7; // Initialize base register
L1 = 18; // Initialize L register
M0 = 8; // Initials to fetch h11
M1 = 6; // initialize to skip 3 element in structured
// element array
P5 = R0; // Address of input array
M3 = R0; // duplicate the address
P0 = R2; // Number of columns (N)
P1 = R2; // Duplicate the number of columns
R6 = R1-R1(NS)||I1+= M0;// Increment to fetch h11 element and clear r6
R7 = 1;
P2 = R1; // Number of rows (M)
P3 = R2; // Number of columns
P0+=-4; // Columns -4
R3 = R2 << 1 ||R0 = B[P5++](Z)||R1.L = W[I1++];
// r3= 2*Col,fetch first input and h11
M0 = R3;
r2 = R7 << 1;
R3 = R3+R2(NS)||P4 = [SP+36];
// Address of output array
M2 = R3; // 2*col +2
P3+= 2; // Col+2
P1+= -2; // Col-2
P2+= -2; // ROW-2;
/////////////////////// FIRST ROW ///////////////////////////////////
// First row and last row is computed separately.
// In each row first and last elements are computed
// separately.
A0 = R0.L*R1.L(IS) || R0 = B[P5++](Z)||R1.L = W[I1++];
// fetch x(0,1) and h12
R2 = W[P5++P1](Z) || R3.L = W[I1++];
// dummy fetches to increment P5 and I1
A0+= R0.L *R1.L(IS) ||R0 = B[P5++](Z) || R1.L = W[I1++];
// fetch x(1,0) and h21
A0+=R0.L*R1.L(IS) ||R0 = B[P5](Z) || R1.L = W[I1++];
// fetch x(1,1) and h22
R2 = (A0+=R0.L * R1.L )(IS)|| I1+= M1;
// Increment I1 to fetch h10
CC = R2==0; // check if result is zero
IF !CC R2 = R7; // if not R2==1
P5 = M3; // Initialize P5 to input array
B[P4++] = R2; // store the result
LSETUP(FIRST_ROW_ST,FIRST_ROW_END)LC0 = P1;
// loop counter == COL-2
FIRST_ROW_ST:
R0 = B[P5++](z) || R1.L = W[I1++];
// fetch X(0,0) and H10
A0 = R0.L *R1.L(IS) ||R0 = B[P5++](z) ||R1.L = W[I1++];
// fetch X(0,1) and H11
A0+=R0.L*R1.L(IS) ||R0 = B[P5] (z)||R1.L = W[I1++];
// fetch X(0,2) and H12
P5 = P5+P1; // increment P5 to fetch x(1,0)
A0+= R0.L *R1.L (IS) ||R0=B[P5++](Z) || R1.L = W[I1++];
// fetch X(1,0) and H20
A0+= R0.L *R1.L (IS)||R0 = B[P5++](z) || R1.L = W[I1++];
// fetch X(1,1) and H21
A0+= R0.L *R1.L(IS) ||R0 = B[P5++](z) || R1.L = W[I1++];
// fetch X(1,2) and H22
R2 = (A0+= R0.L *R1.L)(IS) || I1+= M1;
// Increment I1 to fetch h10
CC = R2 ==0; // check if result is 0
IF !CC R2 = R7; // if not r2 = = 1
P5-= P3;
FIRST_ROW_END:
B[P4++] = R2;
// store the result
R0 = B[P5++](z) || R1.L = W[I1++];
// fetch x(0,N-2) and H10
A0 = R0.L *R1.L (IS) ||R0 = B[P5++](z) || R1.L = W[I1++];
// fetch x(0,n-1) and H11
R2 = W[P5++P1](Z) || R3.L = W[I1++];
// dummy fetch to increment P5 and I1 pointers
A0+= R0.L * R1.L (IS)|| R0 = B[P5++](z) || R1.L = W[I1++];
// fetch x(1,N-2) and H20
A0+= R0.L * R1.L (IS)|| R0 = B[P5++](z)|| R1.L = W[I1++];
// fetch x(1,N-1) and H21
R2 = (A0+= R0.L *R1.L) (IS) ||I1+= 4;
// Increment to fetch h01
CC = R2 == 0;
IF !CC R2 = R7;
P5 = M3; // Initialize P5 to starting of input array
B[P4++] = R2; // store output of last element in first row
//////////// MIDDLE LOOP //////////////////////////////////////////////
P3 = M0; // Initialized to 2*col
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