📄 defbf535.h
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#define P17_IVG12 0x00000050 // Peripheral #17 assigned IVG12
#define P17_IVG13 0x00000060 // Peripheral #17 assigned IVG13
#define P17_IVG14 0x00000070 // Peripheral #17 assigned IVG14
#define P17_IVG15 0x00000080 // Peripheral #17 assigned IVG15
#define P18_IVG7 0x00000000 // Peripheral #18 assigned IVG7
#define P18_IVG8 0x00000100 // Peripheral #18 assigned IVG8
#define P18_IVG9 0x00000200 // Peripheral #18 assigned IVG9
#define P18_IVG10 0x00000300 // Peripheral #18 assigned IVG10
#define P18_IVG11 0x00000400 // Peripheral #18 assigned IVG11
#define P18_IVG12 0x00000500 // Peripheral #18 assigned IVG12
#define P18_IVG13 0x00000600 // Peripheral #18 assigned IVG13
#define P18_IVG14 0x00000700 // Peripheral #18 assigned IVG14
#define P18_IVG15 0x00000800 // Peripheral #18 assigned IVG15
#define P19_IVG7 0x00000000 // Peripheral #19 assigned IVG7
#define P19_IVG8 0x00001000 // Peripheral #19 assigned IVG8
#define P19_IVG9 0x00002000 // Peripheral #19 assigned IVG9
#define P19_IVG10 0x00003000 // Peripheral #19 assigned IVG10
#define P19_IVG11 0x00004000 // Peripheral #19 assigned IVG11
#define P19_IVG12 0x00005000 // Peripheral #19 assigned IVG12
#define P19_IVG13 0x00006000 // Peripheral #19 assigned IVG13
#define P19_IVG14 0x00007000 // Peripheral #19 assigned IVG14
#define P19_IVG15 0x00008000 // Peripheral #19 assigned IVG15
#define P20_IVG7 0x00000000 // Peripheral #20 assigned IVG7
#define P20_IVG8 0x00010000 // Peripheral #20 assigned IVG8
#define P20_IVG9 0x00020000 // Peripheral #20 assigned IVG9
#define P20_IVG10 0x00030000 // Peripheral #20 assigned IVG10
#define P20_IVG11 0x00040000 // Peripheral #20 assigned IVG11
#define P20_IVG12 0x00050000 // Peripheral #20 assigned IVG12
#define P20_IVG13 0x00060000 // Peripheral #20 assigned IVG13
#define P20_IVG14 0x00070000 // Peripheral #20 assigned IVG14
#define P20_IVG15 0x00080000 // Peripheral #20 assigned IVG15
//
// SIC_IMASK Masks
#define SIC_UNMASK_ALL 0x00000000 // Unmask all peripheral interrupts
#define SIC_MASK_ALL 0xFFFFFFFF // Mask all peripheral interrupts
#define SIC_MASK0 0x00000001 // Mask Peripheral #0 interrupt
#define SIC_MASK1 0x00000002 // Mask Peripheral #1 interrupt
#define SIC_MASK2 0x00000004 // Mask Peripheral #2 interrupt
#define SIC_MASK3 0x00000008 // Mask Peripheral #3 interrupt
#define SIC_MASK4 0x00000010 // Mask Peripheral #4 interrupt
#define SIC_MASK5 0x00000020 // Mask Peripheral #5 interrupt
#define SIC_MASK6 0x00000040 // Mask Peripheral #6 interrupt
#define SIC_MASK7 0x00000080 // Mask Peripheral #7 interrupt
#define SIC_MASK8 0x00000100 // Mask Peripheral #8 interrupt
#define SIC_MASK9 0x00000200 // Mask Peripheral #9 interrupt
#define SIC_MASK10 0x00000400 // Mask Peripheral #10 interrupt
#define SIC_MASK11 0x00000800 // Mask Peripheral #11 interrupt
#define SIC_MASK12 0x00001000 // Mask Peripheral #12 interrupt
#define SIC_MASK13 0x00002000 // Mask Peripheral #13 interrupt
#define SIC_MASK14 0x00004000 // Mask Peripheral #14 interrupt
#define SIC_MASK15 0x00008000 // Mask Peripheral #15 interrupt
#define SIC_MASK16 0x00010000 // Mask Peripheral #16 interrupt
#define SIC_MASK17 0x00020000 // Mask Peripheral #17 interrupt
#define SIC_MASK18 0x00040000 // Mask Peripheral #18 interrupt
#define SIC_MASK19 0x00080000 // Mask Peripheral #19 interrupt
#define SIC_MASK20 0x00100000 // Mask Peripheral #20 interrupt
#define SIC_MASK_DFR 0x80000000 // Mask Core Double Fault Reset
#define SIC_UNMASK0 0xFFFFFFFE // Unmask Peripheral #0 interrupt
#define SIC_UNMASK1 0xFFFFFFFD // Unmask Peripheral #1 interrupt
#define SIC_UNMASK2 0xFFFFFFFB // Unmask Peripheral #2 interrupt
#define SIC_UNMASK3 0xFFFFFFF7 // Unmask Peripheral #3 interrupt
#define SIC_UNMASK4 0xFFFFFFEF // Unmask Peripheral #4 interrupt
#define SIC_UNMASK5 0xFFFFFFDF // Unmask Peripheral #5 interrupt
#define SIC_UNMASK6 0xFFFFFFBF // Unmask Peripheral #6 interrupt
#define SIC_UNMASK7 0xFFFFFF7F // Unmask Peripheral #7 interrupt
#define SIC_UNMASK8 0xFFFFFEFF // Unmask Peripheral #8 interrupt
#define SIC_UNMASK9 0xFFFFFDFF // Unmask Peripheral #9 interrupt
#define SIC_UNMASK10 0xFFFFFBFF // Unmask Peripheral #10 interrupt
#define SIC_UNMASK11 0xFFFFF7FF // Unmask Peripheral #11 interrupt
#define SIC_UNMASK12 0xFFFFEFFF // Unmask Peripheral #12 interrupt
#define SIC_UNMASK13 0xFFFFDFFF // Unmask Peripheral #13 interrupt
#define SIC_UNMASK14 0xFFFFBFFF // Unmask Peripheral #14 interrupt
#define SIC_UNMASK15 0xFFFF7FFF // Unmask Peripheral #15 interrupt
#define SIC_UNMASK16 0xFFFEFFFF // Unmask Peripheral #16 interrupt
#define SIC_UNMASK17 0xFFFDFFFF // Unmask Peripheral #17 interrupt
#define SIC_UNMASK18 0xFFFBFFFF // Unmask Peripheral #18 interrupt
#define SIC_UNMASK19 0xFFF7FFFF // Unmask Peripheral #19 interrupt
#define SIC_UNMASK20 0xFFEFFFFF // Unmask Peripheral #20 interrupt
#define SIC_UNMASK_DFR 0x7FFFFFFF // Unmask Core Double Fault Reset
// SIC_IWR Masks
#define IWR_DISABLE_ALL 0x00000000 // Wakeup Disable all peripherals
#define IWR_ENABLE_ALL 0xFFFFFFFF // Wakeup Enable all peripherals
#define IWR_ENABLE0 0x00000001 // Wakeup Enable Peripheral #0
#define IWR_ENABLE1 0x00000002 // Wakeup Enable Peripheral #1
#define IWR_ENABLE2 0x00000004 // Wakeup Enable Peripheral #2
#define IWR_ENABLE3 0x00000008 // Wakeup Enable Peripheral #3
#define IWR_ENABLE4 0x00000010 // Wakeup Enable Peripheral #4
#define IWR_ENABLE5 0x00000020 // Wakeup Enable Peripheral #5
#define IWR_ENABLE6 0x00000040 // Wakeup Enable Peripheral #6
#define IWR_ENABLE7 0x00000080 // Wakeup Enable Peripheral #7
#define IWR_ENABLE8 0x00000100 // Wakeup Enable Peripheral #8
#define IWR_ENABLE9 0x00000200 // Wakeup Enable Peripheral #9
#define IWR_ENABLE10 0x00000400 // Wakeup Enable Peripheral #10
#define IWR_ENABLE11 0x00000800 // Wakeup Enable Peripheral #11
#define IWR_ENABLE12 0x00001000 // Wakeup Enable Peripheral #12
#define IWR_ENABLE13 0x00002000 // Wakeup Enable Peripheral #13
#define IWR_ENABLE14 0x00004000 // Wakeup Enable Peripheral #14
#define IWR_ENABLE15 0x00008000 // Wakeup Enable Peripheral #15
#define IWR_ENABLE16 0x00010000 // Wakeup Enable Peripheral #16
#define IWR_ENABLE17 0x00020000 // Wakeup Enable Peripheral #17
#define IWR_ENABLE18 0x00040000 // Wakeup Enable Peripheral #18
#define IWR_ENABLE19 0x00080000 // Wakeup Enable Peripheral #19
#define IWR_ENABLE20 0x00100000 // Wakeup Enable Peripheral #20
#define IWR_DISABLE0 0xFFFFFFFE // Wakeup Disable Peripheral #0
#define IWR_DISABLE1 0xFFFFFFFD // Wakeup Disable Peripheral #1
#define IWR_DISABLE2 0xFFFFFFFB // Wakeup Disable Peripheral #2
#define IWR_DISABLE3 0xFFFFFFF7 // Wakeup Disable Peripheral #3
#define IWR_DISABLE4 0xFFFFFFEF // Wakeup Disable Peripheral #4
#define IWR_DISABLE5 0xFFFFFFDF // Wakeup Disable Peripheral #5
#define IWR_DISABLE6 0xFFFFFFBF // Wakeup Disable Peripheral #6
#define IWR_DISABLE7 0xFFFFFF7F // Wakeup Disable Peripheral #7
#define IWR_DISABLE8 0xFFFFFEFF // Wakeup Disable Peripheral #8
#define IWR_DISABLE9 0xFFFFFDFF // Wakeup Disable Peripheral #9
#define IWR_DISABLE10 0xFFFFFBFF // Wakeup Disable Peripheral #10
#define IWR_DISABLE11 0xFFFFF7FF // Wakeup Disable Peripheral #11
#define IWR_DISABLE12 0xFFFFEFFF // Wakeup Disable Peripheral #12
#define IWR_DISABLE13 0xFFFFDFFF // Wakeup Disable Peripheral #13
#define IWR_DISABLE14 0xFFFFBFFF // Wakeup Disable Peripheral #14
#define IWR_DISABLE15 0xFFFF7FFF // Wakeup Disable Peripheral #15
#define IWR_DISABLE16 0xFFFEFFFF // Wakeup Disable Peripheral #16
#define IWR_DISABLE17 0xFFFDFFFF // Wakeup Disable Peripheral #17
#define IWR_DISABLE18 0xFFFBFFFF // Wakeup Disable Peripheral #18
#define IWR_DISABLE19 0xFFF7FFFF // Wakeup Disable Peripheral #19
#define IWR_DISABLE20 0xFFEFFFFF // Wakeup Disable Peripheral #20
// WDOGCTL Masks
#define ENABLE_RESET 0x00000000 // Set Watchdog Timer to generate reset
#define ENABLE_NMI 0x00000001 // Set Watchdog Timer to generate non-maskable interrupt
#define ENABLE_GPI 0x00000002 // Set Watchdog Timer to generate general-purpose interrupt
#define DISABLE_EVT 0x00000003 // Disable Watchdog Timer interrupts
// RTCFAST Mask
#define ENABLE_PRESCALE 0x00000001 // Enable prescaler so RTC runs at 1 Hz
// Must be set after power-up for proper operation of RTC
// SPICTLx Masks
#define TIMOD 0x00000003 // Transfer initiation mode and interrupt generation
#define SZ 0x00000004 // Send Zero (=0) or last (=1) word when TDBR empty.
#define GM 0x00000008 // When RDBR full, get more (=1) data or discard (=0) incoming Data
#define PSSE 0x00000010 // Enable (=1) Slave-Select input for Master.
#define EMISO 0x00000020 // Enable (=1) MISO pin as an output.
#define SIZE 0x00000100 // Word length (0 => 8 bits, 1 => 16 bits)
#define LSBF 0x00000200 // Data format (0 => MSB sent/received first 1 => LSB sent/received first)
#define CPHA 0x00000400 // Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer.
#define CPOL 0x00000800 // Clock polarity (0 => active-high, 1 => active-low)
#define MSTR 0x00001000 // Configures SPI as master (=1) or slave (=0)
#define WOM 0x00002000 // Open drain (=1) data output enable (for MOSI and MISO)
#define SPE 0x00004000 // SPI module enable (=1), disable (=0)
// SPIFLGx Masks
#define FLS1 0x00000002 // Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select
#define FLS2 0x00000004 // Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select
#define FLS3 0x00000008 // Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select
#define FLS4 0x00000010 // Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select
#define FLS5 0x00000020 // Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select
#define FLS6 0x00000040 // Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select
#define FLS7 0x00000080 // Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select
#define FLG1 0x00000200 // Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select
#define FLG2 0x00000400 // Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select
#define FLG3 0x00000800 // Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select
#define FLG4 0x00001000 // Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select
#define FLG5 0x00002000 // Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select
#define FLG6 0x00004000 // Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select
#define FLG7 0x00008000 // Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select
// SPIFLGx Bit Positions
#define FLS1_P 0x00000001 // Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select
#define FLS2_P 0x00000002 // Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select
#define FLS3_P 0x00000003 // Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select
#define FLS4_P 0x00000004 // Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select
#define FLS5_P 0x00000005 // Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select
#define FLS6_P 0x00000006 // Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select
#define FLS7_P 0x00000007 // Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select
#define FLG1_P 0x00000009 // Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select
#define FLG2_P 0x0000000A // Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select
#define FLG3_P 0x0000000B // Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select
#define FLG4_P 0x0000000C // Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select
#define FLG5_P 0x0000000D // Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select
#define FLG6_P 0x0000000E // Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select
#define FLG7_P 0x0000000F // Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select
// AMGCTL Masks
#define AMCKEN 0x00000001 // Enable CLKOUT
#define AMBEN_B4 0x00000002 // Enable Asynchronous Memory Bank 6 only
#define AMBEN_B4_B5 0x00000004 // Enable Asynchronous Memory Banks 4 & 5 only
#define AMBEN_ALL 0x00000006 // Enable Asynchronous Memory Banks (all) 4, 5, 6, and 7
#define B4PEN 0x00000010 // Enable 16-bit packing for Asynchronous Memory Bank 4
#define B5PEN 0x00000020 // Enable 16-bit packing for Asynchronous Memory Bank 5
#define B6PEN 0x00000040 // Enable 16-bit packing for Asynchronous Memory Bank 6
#define B7PEN 0x00000080 // Enable 16-bit packing for Asynchronous Memory Bank 7
// AMGCTL Bit Positions
#define AMCKEN_P 0x00000000 // Enable CLKOUT
#define AMBEN_P0 0x00000001 // Asynchronous Memory Enable, 00 - banks 4-7 disabled, 01 - bank 4 enabled
#define AMBEN_P1 0x00000002 // Asynchronous Memory Enable, 10 - banks 4&5 enabled, 11 - banks 4-7 enabled
#define B4PEN_P 0x00000004 // Enable 16-bit packing for Asynchronous Memory Bank 4
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