defbf535.h

ADI BF DSP PCI接口代码

// PLLCTL Masks
#define PLL_CLKIN              0x00000000  // Pass CLKIN to PLL
#define PLL_CLKIN_DIV2         0x00000001  // Pass CLKIN/2 to PLL
#define PLL_OFF                0x00000002  // Shut off PLL clocks
#define STOPCK_OFF             0x00000008  // Core clock off
#define PDWN                   0x00000020  // Put the PLL in a Deep Sleep state
#define BYPASS                 0x00000100  // Bypass the PLL
#define CCLK_DIV2              0x00000000  // SCLK = CCLK / 2
#define CCLK_DIV2_5            0x00010000  // SCLK = CCLK / 2.5
#define CCLK_DIV3              0x00020000  // SCLK = CCLK / 3
#define CCLK_DIV4              0x00030000  // SCLK = CCLK / 4

// IOCKR Masks
#define IOCK_PCI               0x00000001  // Enable PCI peripheral clock
#define IOCK_L2                0x00000002  // Enable L2 memory peripheral clock
#define IOCK_EBIU              0x00000004  // Enable EBIU controller peripheral clock
#define IOCK_GPIO              0x00000008  // Enable GPIO peripheral clock
#define IOCK_MEMDMA            0x00000010  // Enable MemDMA controller peripheral clock
#define IOCK_SPORT0            0x00000020  // Enable SPORT0 controller peripheral clock
#define IOCK_SPORT1            0x00000040  // Enable SPORT1 controller peripheral clock
#define IOCK_SPI0              0x00000080  // Enable SPI0 controller peripheral clock
#define IOCK_SPI1              0x00000100  // Enable SPI1 controller peripheral clock
#define IOCK_UART0             0x00000200  // Enable UART0 controller peripheral clock
#define IOCK_UART1             0x00000400  // Enable UART1 controller peripheral clock
#define IOCK_TIMER0            0x00000800  // Enable TIMER0 peripheral clock
#define IOCK_TIMER1            0x00001000  // Enable TIMER1 peripheral clock
#define IOCK_TIMER2            0x00002000  // Enable TIMER2 peripheral clock
#define IOCK_USB               0x00004000  // Enable USB peripheral clock

// SWRST Mask
#define SYSTEM_RESET           0x00000007  // Initiates a system software reset

// System Interrupt Controller Masks (SIC_IAR0, SIC_IAR1, SIC_IAR2, SIC_IMASK, SIC_IWR)
// SIC_IAR0 Masks

//
#define P0_IVG7                0x00000000  // Peripheral #0 assigned IVG7
#define P0_IVG8                0x00000001  // Peripheral #0 assigned IVG8
#define P0_IVG9                0x00000002  // Peripheral #0 assigned IVG9
#define P0_IVG10               0x00000003  // Peripheral #0 assigned IVG10
#define P0_IVG11               0x00000004  // Peripheral #0 assigned IVG11
#define P0_IVG12               0x00000005  // Peripheral #0 assigned IVG12
#define P0_IVG13               0x00000006  // Peripheral #0 assigned IVG13
#define P0_IVG14               0x00000007  // Peripheral #0 assigned IVG14
#define P0_IVG15               0x00000008  // Peripheral #0 assigned IVG15
#define P1_IVG7                0x00000000  // Peripheral #1 assigned IVG7
#define P1_IVG8                0x00000010  // Peripheral #1 assigned IVG8
#define P1_IVG9                0x00000020  // Peripheral #1 assigned IVG9
#define P1_IVG10               0x00000030  // Peripheral #1 assigned IVG10
#define P1_IVG11               0x00000040  // Peripheral #1 assigned IVG11
#define P1_IVG12               0x00000050  // Peripheral #1 assigned IVG12
#define P1_IVG13               0x00000060  // Peripheral #1 assigned IVG13
#define P1_IVG14               0x00000070  // Peripheral #1 assigned IVG14
#define P1_IVG15               0x00000080  // Peripheral #1 assigned IVG15
#define P2_IVG7                0x00000000  // Peripheral #2 assigned IVG7
#define P2_IVG8                0x00000100  // Peripheral #2 assigned IVG8
#define P2_IVG9                0x00000200  // Peripheral #2 assigned IVG9
#define P2_IVG10               0x00000300  // Peripheral #2 assigned IVG10
#define P2_IVG11               0x00000400  // Peripheral #2 assigned IVG11
#define P2_IVG12               0x00000500  // Peripheral #2 assigned IVG12
#define P2_IVG13               0x00000600  // Peripheral #2 assigned IVG13
#define P2_IVG14               0x00000700  // Peripheral #2 assigned IVG14
#define P2_IVG15               0x00000800  // Peripheral #2 assigned IVG15
#define P3_IVG7                0x00000000  // Peripheral #3 assigned IVG7
#define P3_IVG8                0x00001000  // Peripheral #3 assigned IVG8
#define P3_IVG9                0x00002000  // Peripheral #3 assigned IVG9
#define P3_IVG10               0x00003000  // Peripheral #3 assigned IVG10
#define P3_IVG11               0x00004000  // Peripheral #3 assigned IVG11
#define P3_IVG12               0x00005000  // Peripheral #3 assigned IVG12
#define P3_IVG13               0x00006000  // Peripheral #3 assigned IVG13
#define P3_IVG14               0x00007000  // Peripheral #3 assigned IVG14
#define P3_IVG15               0x00008000  // Peripheral #3 assigned IVG15
#define P4_IVG7                0x00000000  // Peripheral #4 assigned IVG7
#define P4_IVG8                0x00010000  // Peripheral #4 assigned IVG8
#define P4_IVG9                0x00020000  // Peripheral #4 assigned IVG9
#define P4_IVG10               0x00030000  // Peripheral #4 assigned IVG10
#define P4_IVG11               0x00040000  // Peripheral #4 assigned IVG11
#define P4_IVG12               0x00050000  // Peripheral #4 assigned IVG12
#define P4_IVG13               0x00060000  // Peripheral #4 assigned IVG13
#define P4_IVG14               0x00070000  // Peripheral #4 assigned IVG14
#define P4_IVG15               0x00080000  // Peripheral #4 assigned IVG15
#define P5_IVG7                0x00000000  // Peripheral #5 assigned IVG7
#define P5_IVG8                0x00100000  // Peripheral #5 assigned IVG8
#define P5_IVG9                0x00200000  // Peripheral #5 assigned IVG9
#define P5_IVG10               0x00300000  // Peripheral #5 assigned IVG10
#define P5_IVG11               0x00400000  // Peripheral #5 assigned IVG11
#define P5_IVG12               0x00500000  // Peripheral #5 assigned IVG12
#define P5_IVG13               0x00600000  // Peripheral #5 assigned IVG13
#define P5_IVG14               0x00700000  // Peripheral #5 assigned IVG14
#define P5_IVG15               0x00800000  // Peripheral #5 assigned IVG15
#define P6_IVG7                0x00000000  // Peripheral #6 assigned IVG7
#define P6_IVG8                0x01000000  // Peripheral #6 assigned IVG8
#define P6_IVG9                0x02000000  // Peripheral #6 assigned IVG9
#define P6_IVG10               0x03000000  // Peripheral #6 assigned IVG10
#define P6_IVG11               0x04000000  // Peripheral #6 assigned IVG11
#define P6_IVG12               0x05000000  // Peripheral #6 assigned IVG12
#define P6_IVG13               0x06000000  // Peripheral #6 assigned IVG13
#define P6_IVG14               0x07000000  // Peripheral #6 assigned IVG14
#define P6_IVG15               0x08000000  // Peripheral #6 assigned IVG15
#define P7_IVG7                0x00000000  // Peripheral #7 assigned IVG7
#define P7_IVG8                0x10000000  // Peripheral #7 assigned IVG8
#define P7_IVG9                0x20000000  // Peripheral #7 assigned IVG9
#define P7_IVG10               0x30000000  // Peripheral #7 assigned IVG10
#define P7_IVG11               0x40000000  // Peripheral #7 assigned IVG11
#define P7_IVG12               0x50000000  // Peripheral #7 assigned IVG12
#define P7_IVG13               0x60000000  // Peripheral #7 assigned IVG13
#define P7_IVG14               0x70000000  // Peripheral #7 assigned IVG14
#define P7_IVG15               0x80000000  // Peripheral #7 assigned IVG15

// SIC_IAR1 Masks
#define P8_IVG7                0x00000000  // Peripheral #8 assigned IVG7
#define P8_IVG8                0x00000001  // Peripheral #8 assigned IVG8
#define P8_IVG9                0x00000002  // Peripheral #8 assigned IVG9
#define P8_IVG10               0x00000003  // Peripheral #8 assigned IVG10
#define P8_IVG11               0x00000004  // Peripheral #8 assigned IVG11
#define P8_IVG12               0x00000005  // Peripheral #8 assigned IVG12
#define P8_IVG13               0x00000006  // Peripheral #8 assigned IVG13
#define P8_IVG14               0x00000007  // Peripheral #8 assigned IVG14
#define P8_IVG15               0x00000008  // Peripheral #8 assigned IVG15
#define P9_IVG7                0x00000000  // Peripheral #9 assigned IVG7
#define P9_IVG8                0x00000010  // Peripheral #9 assigned IVG8
#define P9_IVG9                0x00000020  // Peripheral #9 assigned IVG9
#define P9_IVG10               0x00000030  // Peripheral #9 assigned IVG10
#define P9_IVG11               0x00000040  // Peripheral #9 assigned IVG11
#define P9_IVG12               0x00000050  // Peripheral #9 assigned IVG12
#define P9_IVG13               0x00000060  // Peripheral #9 assigned IVG13
#define P9_IVG14               0x00000070  // Peripheral #9 assigned IVG14
#define P9_IVG15               0x00000080  // Peripheral #9 assigned IVG15
#define P10_IVG7               0x00000000  // Peripheral #10 assigned IVG7
#define P10_IVG8               0x00000100  // Peripheral #10 assigned IVG8
#define P10_IVG9               0x00000200  // Peripheral #10 assigned IVG9
#define P10_IVG10              0x00000300  // Peripheral #10 assigned IVG10
#define P10_IVG11              0x00000400  // Peripheral #10 assigned IVG11
#define P10_IVG12              0x00000500  // Peripheral #10 assigned IVG12
#define P10_IVG13              0x00000600  // Peripheral #10 assigned IVG13
#define P10_IVG14              0x00000700  // Peripheral #10 assigned IVG14
#define P10_IVG15              0x00000800  // Peripheral #10 assigned IVG15
#define P11_IVG7               0x00000000  // Peripheral #11 assigned IVG7
#define P11_IVG8               0x00001000  // Peripheral #11 assigned IVG8
#define P11_IVG9               0x00002000  // Peripheral #11 assigned IVG9
#define P11_IVG10              0x00003000  // Peripheral #11 assigned IVG10
#define P11_IVG11              0x00004000  // Peripheral #11 assigned IVG11
#define P11_IVG12              0x00005000  // Peripheral #11 assigned IVG12
#define P11_IVG13              0x00006000  // Peripheral #11 assigned IVG13
#define P11_IVG14              0x00007000  // Peripheral #11 assigned IVG14
#define P11_IVG15              0x00008000  // Peripheral #11 assigned IVG15
#define P12_IVG7               0x00000000  // Peripheral #12 assigned IVG7
#define P12_IVG8               0x00010000  // Peripheral #12 assigned IVG8
#define P12_IVG9               0x00020000  // Peripheral #12 assigned IVG9
#define P12_IVG10              0x00030000  // Peripheral #12 assigned IVG10
#define P12_IVG11              0x00040000  // Peripheral #12 assigned IVG11
#define P12_IVG12              0x00050000  // Peripheral #12 assigned IVG12
#define P12_IVG13              0x00060000  // Peripheral #12 assigned IVG13
#define P12_IVG14              0x00070000  // Peripheral #12 assigned IVG14
#define P12_IVG15              0x00080000  // Peripheral #12 assigned IVG15
#define P13_IVG7               0x00000000  // Peripheral #13 assigned IVG7
#define P13_IVG8               0x00100000  // Peripheral #13 assigned IVG8
#define P13_IVG9               0x00200000  // Peripheral #13 assigned IVG9
#define P13_IVG10              0x00300000  // Peripheral #13 assigned IVG10
#define P13_IVG11              0x00400000  // Peripheral #13 assigned IVG11
#define P13_IVG12              0x00500000  // Peripheral #13 assigned IVG12
#define P13_IVG13              0x00600000  // Peripheral #13 assigned IVG13
#define P13_IVG14              0x00700000  // Peripheral #14 assigned IVG14
#define P13_IVG15              0x00800000  // Peripheral #14 assigned IVG15
#define P14_IVG7               0x00000000  // Peripheral #14 assigned IVG7
#define P14_IVG8               0x01000000  // Peripheral #14 assigned IVG8
#define P14_IVG9               0x02000000  // Peripheral #14 assigned IVG9
#define P14_IVG10              0x03000000  // Peripheral #14 assigned IVG10
#define P14_IVG11              0x04000000  // Peripheral #14 assigned IVG11
#define P14_IVG12              0x05000000  // Peripheral #14 assigned IVG12
#define P14_IVG13              0x06000000  // Peripheral #14 assigned IVG13
#define P14_IVG14              0x07000000  // Peripheral #14 assigned IVG14
#define P14_IVG15              0x08000000  // Peripheral #14 assigned IVG15
#define P15_IVG7               0x00000000  // Peripheral #15 assigned IVG7
#define P15_IVG8               0x10000000  // Peripheral #15 assigned IVG8
#define P15_IVG9               0x20000000  // Peripheral #15 assigned IVG9
#define P15_IVG10              0x30000000  // Peripheral #15 assigned IVG10
#define P15_IVG11              0x40000000  // Peripheral #15 assigned IVG11
#define P15_IVG12              0x50000000  // Peripheral #15 assigned IVG12
#define P15_IVG13              0x60000000  // Peripheral #15 assigned IVG13
#define P15_IVG14              0x70000000  // Peripheral #15 assigned IVG14
#define P15_IVG15              0x80000000  // Peripheral #15 assigned IVG15

// SIC_IAR2 Masks
#define P16_IVG7               0x00000000  // Peripheral #16 assigned IVG7
#define P16_IVG8               0x00000001  // Peripheral #16 assigned IVG8
#define P16_IVG9               0x00000002  // Peripheral #16 assigned IVG9
#define P16_IVG10              0x00000003  // Peripheral #16 assigned IVG10
#define P16_IVG11              0x00000004  // Peripheral #16 assigned IVG11
#define P16_IVG12              0x00000005  // Peripheral #16 assigned IVG12
#define P16_IVG13              0x00000006  // Peripheral #16 assigned IVG13
#define P16_IVG14              0x00000007  // Peripheral #16 assigned IVG14
#define P16_IVG15              0x00000008  // Peripheral #16 assigned IVG15
#define P17_IVG7               0x00000000  // Peripheral #17 assigned IVG7
#define P17_IVG8               0x00000010  // Peripheral #17 assigned IVG8
#define P17_IVG9               0x00000020  // Peripheral #17 assigned IVG9
#define P17_IVG10              0x00000030  // Peripheral #17 assigned IVG10
#define P17_IVG11              0x00000040  // Peripheral #17 assigned IVG11