📄 defbf535.h
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#define MDD_DCP 0xFFC03800 // Current Pointer - Write Channel
#define MDD_DCFG 0xFFC03802 // DMA Configuration - Write Channel
#define MDD_DSAH 0xFFC03804 // Start Address Hi - Write Channel
#define MDD_DSAL 0xFFC03806 // Start Address Lo - Write Channel
#define MDD_DCT 0xFFC03808 // DMA Count - Write Channel
#define MDD_DND 0xFFC0380A // Next Descriptor Pointer - Write Channel
#define MDD_DDR 0xFFC0380C // Descriptor Ready - Write Channel
#define MDD_DI 0xFFC0380E // DMA Interrupt - Write Channel
#define MDS_DCP 0xFFC03900 // Current Pointer - Read Channel
#define MDS_DCFG 0xFFC03902 // DMA Configuration - Read Channel
#define MDS_DSAH 0xFFC03904 // Start Address Hi - Read Channel
#define MDS_DSAL 0xFFC03906 // Start Address Lo - Read Channel
#define MDS_DCT 0xFFC03908 // DMA Count - Read Channel
#define MDS_DND 0xFFC0390A // Next Descriptor Pointer - Read Channel
#define MDS_DDR 0xFFC0390C // Descriptor Ready - Read Channel
#define MDS_DI 0xFFC0390E // DMA Interrupt - Read Channel
// For backwards-compatibility with VDSP++3.0 and earlier code...
#define MDW_DCP MDD_DCP
#define MDW_DCFG MDD_DCFG
#define MDW_DSAH MDD_DSAH
#define MDW_DSAL MDD_DSAL
#define MDW_DCT MDD_DCT
#define MDW_DND MDD_DND
#define MDW_DDR MDD_DDR
#define MDW_DI MDD_DI
#define MDR_DCP MDS_DCP
#define MDR_DCFG MDS_DCFG
#define MDR_DSAH MDS_DSAH
#define MDR_DSAL MDS_DSAL
#define MDR_DCT MDS_DCT
#define MDR_DND MDS_DND
#define MDR_DDR MDS_DDR
#define MDR_DI MDS_DI
// Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF)
#define EBIU_AMGCTL 0xFFC03C00 // Asynchronous Memory Global Control Register
#define EBIU_AMBCTL0 0xFFC03C04 // Asynchronous Memory Bank Control Register 0
#define EBIU_AMBCTL1 0xFFC03C08 // Asynchronous Memory Bank Control Register 1
// PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF)
#define PCI_CTL 0xFFC04000 // PCI Bridge Control
#define PCI_CTL_HOST 0x01
#define PCI_CTL_ENABPCI 0x02
#define PCI_CTL_FASTBCK2BCK 0x04
#define PCI_CTL_ENABINTA 0x08
#define PCI_CTL_OUTPUTINTA 0x10
#define PCI_CTL_ENABRST 0x20
#define PCI_CTL_OUTPUTRST 0x40
#define PCI_STAT 0xFFC04004 // PCI Bridge Status
#define PCI_STAT_INTA 0x0001
#define PCI_STAT_INTB 0x0002
#define PCI_STAT_INTC 0x0004
#define PCI_STAT_INTD 0x0008
#define PCI_STAT_PARERR 0x0010
#define PCI_STAT_FATERR 0x0020
#define PCI_STAT_RESET 0x0040
#define PCI_STAT_TXEMPTY 0x0080
#define PCI_STAT_TXFULL 0x0100
#define PCI_STAT_QUEFULL 0x0200
#define PCI_STAT_MEMWRINV 0x0400
#define PCI_STAT_INRDERR 0x0800
#define PCI_STAT_INWRERR 0x1000
#define PCI_STAT_INVEABACC 0x2000
#define PCI_STAT_SYSERR 0x4000
#define PCI_ICTL 0xFFC04008 // PCI Bridge Interrupt Control
#define PCI_ICTL_INTA 0x0001
#define PCI_ICTL_INTB 0x0002
#define PCI_ICTL_INTC 0x0004
#define PCI_ICTL_INTD 0x0008
#define PCI_ICTL_PARERR 0x0010
#define PCI_ICTL_FATERR 0x0020
#define PCI_ICTL_RESET 0x0040
#define PCI_ICTL_TXFULL 0x0080
#define PCI_ICTL_MEMWRINV 0x0400
#define PCI_ICTL_INRDERR 0x0800
#define PCI_ICTL_INWRERR 0x1000
#define PCI_ICTL_INVEABACC 0x2000
#define PCI_ICTL_SYSERR 0x4000
#define PCI_MBAP 0xFFC0400C // PCI Memory Space Base Address Pointer [31:27]
#define PCI_IBAP 0xFFC04010 // PCI IO Space Base Address Pointer
#define PCI_CBAP 0xFFC04014 // PCI Config Space Base Address Port
#define PCI_TMBAP 0xFFC04018 // PCI to BF535 Memory Base Address Pointer
#define PCI_TIBAP 0xFFC0401C // PCI to BF535 IO Base Address Pointer
// PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF)
#define PCI_DMBARM 0xEEFFFF00 // PCI Device Memory Bar Mask
#define PCI_DIBARM 0xEEFFFF04 // PCI Device IO Bar Mask
#define PCI_CFG_DIC 0xEEFFFF08 // PCI Config Device ID
#define PCI_CFG_VIC 0xEEFFFF0C // PCI Config Vendor ID
#define PCI_CFG_STAT 0xEEFFFF10 // PCI Config Status (Read-only)
#define PCI_CFG_CMD 0xEEFFFF14 // PCI Config Command
#define PCI_CFG_CC 0xEEFFFF18 // PCI Config Class Code
#define PCI_CFG_RID 0xEEFFFF1C // PCI Config Revision ID
#define PCI_CFG_BIST 0xEEFFFF20 // PCI Config BIST
#define PCI_CFG_HT 0xEEFFFF24 // PCI Config Header Type
#define PCI_CFG_MLT 0xEEFFFF28 // PCI Config Memory Latency Timer
#define PCI_CFG_CLS 0xEEFFFF2C // PCI Config Cache Line Size
#define PCI_CFG_MBAR 0xEEFFFF30 // PCI Config Memory Base Address Register
#define PCI_CFG_IBAR 0xEEFFFF34 // PCI Config IO Base Address Register
#define PCI_CFG_SID 0xEEFFFF38 // PCI Config Sub-system ID
#define PCI_CFG_SVID 0xEEFFFF3C // PCI Config Sub-system Vendor ID
#define PCI_CFG_MAXL 0xEEFFFF40 // PCI Config Maximum Latency Cycles
#define PCI_CFG_MING 0xEEFFFF44 // PCI Config Minimum Grant Cycles
#define PCI_CFG_IP 0xEEFFFF48 // PCI Config Interrupt Pin
#define PCI_CFG_IL 0xEEFFFF4C // PCI Config Interrupt Line
#define PCI_HMCTL 0xEEFFFF50 // PCI Blocking BAR Host Mode Control
#define PCI_HMCTL_SYSMMRENAB 0x1
#define PCI_HMCTL_L2ENAB 0x2
#define PCI_HMCTL_ASYNCENAB 0x4
#define PCI_HMCTL_ASYNCSIZE 0x18 /* 00-64MB, 01-128MB, 10-192MB, 11-256MB */
#define PCI_HMCTL_SDRAMENAB 0x20
#define PCI_HMCTL_SDRAMSIZE 0x7C0 /* 0-32MB, 1-64MB, 2-96MB, 128MB, 160MB */
// USB Registers (0xFFC0 4400 - 0xFFC0 47FF)
#define USBD_ID 0xFFC04400 // USB Device ID Register
#define USBD_FRM 0xFFC04402 // Current USB Frame Number
#define USBD_FRMAT 0xFFC04404 // Match value for USB frame number.
#define USBD_EPBUF 0xFFC04406 // Enables Download of Configuration Into UDC Core
#define USBD_STAT 0xFFC04408 // Returns USBD Module Status
#define USBD_CTRL 0xFFC0440A // Allows Configuration and Control of USBD Module.
#define USBD_GINTR 0xFFC0440C // Global Interrupt Register
#define USBD_GMASK 0xFFC0440E // Global Interrupt Register Mask
#define USBD_DMACFG 0xFFC04440 // DMA Master Channel Configuration Register
#define USBD_DMABL 0xFFC04442 // DMA Master Channel Base Address, Low
#define USBD_DMABH 0xFFC04444 // DMA Master Channel Base Address, High
#define USBD_DMACT 0xFFC04446 // DMA Master Channel Count Register
#define USBD_DMAIRQ 0xFFC04448 // DMA Master Channel DMA Count Register
#define USBD_INTR0 0xFFC04480 // USB Endpoint 0 Interrupt Register
#define USBD_MASK0 0xFFC04482 // USB Endpoint 0 Mask Register
#define USBD_EPCFG0 0xFFC04484 // USB Endpoint 0 Control Register
#define USBD_EPADR0 0xFFC04486 // USB Endpoint 0 Address Offset Register
#define USBD_EPLEN0 0xFFC04488 // USB Endpoint 0 Buffer Length Register
#define USBD_INTR1 0xFFC0448A // USB Endpoint 1 Interrupt Register
#define USBD_MASK1 0xFFC0448C // USB Endpoint 1 Mask Register
#define USBD_EPCFG1 0xFFC0448E // USB Endpoint 1 Control Register
#define USBD_EPADR1 0xFFC04490 // USB Endpoint 1 Address Offset Register
#define USBD_EPLEN1 0xFFC04492 // USB Endpoint 1 Buffer Length Register
#define USBD_INTR2 0xFFC04494 // USB Endpoint 2 Interrupt Register
#define USBD_MASK2 0xFFC04496 // USB Endpoint 2 Mask Register
#define USBD_EPCFG2 0xFFC04498 // USB Endpoint 2 Control Register
#define USBD_EPADR2 0xFFC0449A // USB Endpoint 2 Address Offset Register
#define USBD_EPLEN2 0xFFC0449C // USB Endpoint 2 Buffer Length Register
#define USBD_INTR3 0xFFC0449E // USB Endpoint 3 Interrupt Register
#define USBD_MASK3 0xFFC044A0 // USB Endpoint 3 Mask Register
#define USBD_EPCFG3 0xFFC044A2 // USB Endpoint 3 Control Register
#define USBD_EPADR3 0xFFC044A4 // USB Endpoint 3 Address Offset Register
#define USBD_EPLEN3 0xFFC044A6 // USB Endpoint 3 Buffer Length Register
#define USBD_INTR4 0xFFC044A8 // USB Endpoint 4 Interrupt Register
#define USBD_MASK4 0xFFC044AA // USB Endpoint 4 Mask Register
#define USBD_EPCFG4 0xFFC044AC // USB Endpoint 4 Control Register
#define USBD_EPADR4 0xFFC044AE // USB Endpoint 4 Address Offset Register
#define USBD_EPLEN4 0xFFC044B0 // USB Endpoint 4 Buffer Length Register
#define USBD_INTR5 0xFFC044B2 // USB Endpoint 5 Interrupt Register
#define USBD_MASK5 0xFFC044B4 // USB Endpoint 5 Mask Register
#define USBD_EPCFG5 0xFFC044B6 // USB Endpoint 5 Control Register
#define USBD_EPADR5 0xFFC044B8 // USB Endpoint 5 Address Offset Register
#define USBD_EPLEN5 0xFFC044BA // USB Endpoint 5 Buffer Length Register
#define USBD_INTR6 0xFFC044BC // USB Endpoint 6 Interrupt Register
#define USBD_MASK6 0xFFC044BE // USB Endpoint 6 Mask Register
#define USBD_EPCFG6 0xFFC044C0 // USB Endpoint 6 Control Register
#define USBD_EPADR6 0xFFC044C2 // USB Endpoint 6 Address Offset Register
#define USBD_EPLEN6 0xFFC044C4 // USB Endpoint 6 Buffer Length Register
#define USBD_INTR7 0xFFC044C6 // USB Endpoint 7 Interrupt Register
#define USBD_MASK7 0xFFC044C8 // USB Endpoint 7 Mask Register
#define USBD_EPCFG7 0xFFC044CA // USB Endpoint 7 Control Register
#define USBD_EPADR7 0xFFC044CC // USB Endpoint 7 Address Offset Register
#define USBD_EPLEN7 0xFFC044CE // USB Endpoint 7 Buffer Length Register
// System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF)
#define L1SBAR 0xFFC04840 // L1 SRAM Base Address Register
#define L1CSR 0xFFC04844 // L1 SRAM Control Initialization Register
#define DMA_DBP 0xFFC04880 // Next Descriptor Base Pointer
#define DB_ACOMP 0xFFC04884 // DMA Bus Address Comparator
#define DB_CCOMP 0xFFC04888 // DMA Bus Control Comparator
#define DB_NDBP DMA_DBP // Backward compatibility
#define L1_SBAR L1SBAR
#define L1_CSR L1CSR
// SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF)
#define EBIU_SDGCTL 0xFFC04C00 // SDRAM Global Control Register
#define EBIU_SDBCTL 0xFFC04C04 // SDRAM Bank Control Register
#define EBIU_SDRRC 0xFFC04C0A // SDRAM Refresh Rate Control Register
#define EBIU_SDSTAT 0xFFC04C0E // SDRAM Status Register
// PAB Reserved (0xFFC0 5000-0xFFDF FFFF) (**Reserved**)
//**********************************************************************************
// System MMR Register Bits
//**********************************************************************************
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