pci_ids.h

ADI BF DSP PCI接口代码

/****************************************************************

  $Header: /proj/ras/CVS/utils/hardware/adsp-BF535/include/pci_ids.h,v 1.1.1.1 2001/09/09 00:06:39 rmishra Exp $

  Copyright (c) 2001 Analog Devices Inc.  
  All rights reserved.

  MODULE:	pci_ids.h

  DESCRIPTION:	PCI Class, Vendor and Device IDs

  REVISION HISTORY:

  $Log: pci_ids.h,v $
  Revision 1.1.1.1  2001/09/09 00:06:39  rmishra
  BlackFin ADSP-BF535 hardware debug


*************************************************************/

#ifndef _PCI_IDS_H_
#define _PCI_IDS_H_

/* Device classes and subclasses */

#define PCI_CLASS_NOT_DEFINED		0x0000
#define PCI_CLASS_NOT_DEFINED_VGA	0x0001

#define PCI_BASE_CLASS_STORAGE		0x01
#define PCI_CLASS_STORAGE_SCSI		0x0100
#define PCI_CLASS_STORAGE_IDE		0x0101
#define PCI_CLASS_STORAGE_FLOPPY	0x0102
#define PCI_CLASS_STORAGE_IPI		0x0103
#define PCI_CLASS_STORAGE_RAID		0x0104
#define PCI_CLASS_STORAGE_OTHER		0x0180

#define PCI_BASE_CLASS_NETWORK		0x02
#define PCI_CLASS_NETWORK_ETHERNET	0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
#define PCI_CLASS_NETWORK_FDDI		0x0202
#define PCI_CLASS_NETWORK_ATM		0x0203
#define PCI_CLASS_NETWORK_OTHER		0x0280

#define PCI_BASE_CLASS_DISPLAY		0x03
#define PCI_CLASS_DISPLAY_VGA		0x0300
#define PCI_CLASS_DISPLAY_XGA		0x0301
#define PCI_CLASS_DISPLAY_3D		0x0302
#define PCI_CLASS_DISPLAY_OTHER		0x0380

#define PCI_BASE_CLASS_MULTIMEDIA	0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480

#define PCI_BASE_CLASS_MEMORY		0x05
#define PCI_CLASS_MEMORY_RAM		0x0500
#define PCI_CLASS_MEMORY_FLASH		0x0501
#define PCI_CLASS_MEMORY_OTHER		0x0580

#define PCI_BASE_CLASS_BRIDGE		0x06
#define PCI_CLASS_BRIDGE_HOST		0x0600
#define PCI_CLASS_BRIDGE_ISA		0x0601
#define PCI_CLASS_BRIDGE_EISA		0x0602
#define PCI_CLASS_BRIDGE_MC			0x0603
#define PCI_CLASS_BRIDGE_PCI		0x0604
#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
#define PCI_CLASS_BRIDGE_NUBUS		0x0606
#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
#define PCI_CLASS_BRIDGE_OTHER		0x0680

#define PCI_BASE_CLASS_COMMUNICATION		0x07
#define PCI_CLASS_COMMUNICATION_SERIAL		0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 	0x0701
#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
#define PCI_CLASS_COMMUNICATION_MODEM		0x0703
#define PCI_CLASS_COMMUNICATION_OTHER		0x0780

#define PCI_BASE_CLASS_SYSTEM			0x08
#define PCI_CLASS_SYSTEM_PIC			0x0800
#define PCI_CLASS_SYSTEM_DMA			0x0801
#define PCI_CLASS_SYSTEM_TIMER			0x0802
#define PCI_CLASS_SYSTEM_RTC			0x0803
#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
#define PCI_CLASS_SYSTEM_OTHER			0x0880

#define PCI_BASE_CLASS_INPUT		0x09
#define PCI_CLASS_INPUT_KEYBOARD	0x0900
#define PCI_CLASS_INPUT_PEN			0x0901
#define PCI_CLASS_INPUT_MOUSE		0x0902
#define PCI_CLASS_INPUT_SCANNER		0x0903
#define PCI_CLASS_INPUT_GAMEPORT	0x0904
#define PCI_CLASS_INPUT_OTHER		0x0980

#define PCI_BASE_CLASS_DOCKING		0x0a
#define PCI_CLASS_DOCKING_GENERIC	0x0a00
#define PCI_CLASS_DOCKING_OTHER		0x0a80

#define PCI_BASE_CLASS_PROCESSOR	0x0b
#define PCI_CLASS_PROCESSOR_386		0x0b00
#define PCI_CLASS_PROCESSOR_486		0x0b01
#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
#define PCI_CLASS_PROCESSOR_CO		0x0b40

#define PCI_BASE_CLASS_SERIAL		0x0c
#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
#define PCI_CLASS_SERIAL_ACCESS		0x0c01
#define PCI_CLASS_SERIAL_SSA		0x0c02
#define PCI_CLASS_SERIAL_USB		0x0c03
#define PCI_CLASS_SERIAL_FIBER		0x0c04
#define PCI_CLASS_SERIAL_SMBUS		0x0c05

#define PCI_BASE_CLASS_INTELLIGENT	0x0e
#define PCI_CLASS_INTELLIGENT_I2O	0x0e00

#define PCI_BASE_CLASS_SATELLITE	0x0f
#define PCI_CLASS_SATELLITE_TV		0x0f00
#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
#define PCI_CLASS_SATELLITE_VOICE	0x0f03
#define PCI_CLASS_SATELLITE_DATA	0x0f04

#define PCI_BASE_CLASS_CRYPT			0x10
#define PCI_CLASS_CRYPT_NETWORK			0x1000
#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
#define PCI_CLASS_CRYPT_OTHER			0x1080

#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
#define PCI_CLASS_SP_DPIO		0x1100
// #define PCI_CLASS_SP_OTHER		0x1180 
#define PCI_CLASS_SP_OTHER		0x8000  /* 02/05/02 JM: Sub-Class 0x80 and Interface 0x00 per PCI 2.2 spec */


#define PCI_CLASS_OTHERS		0xff

#define PCI_VENDOR_ID_ADI		0x11d4
#define PCI_DEVICE_ID_ADSP21535		0x1535	/* jm  default device ID on rev 1.0 silicon */


/*****************************************************************/

#define SDRAM_NUM_BANKS	1		/* only 1 bank populated */
#define SDRAM_SIZE	0x1000000	/* 16 MB */

/*
 * PCI target definitions
 */
#define PCI_VENDOR_ID	PCI_VENDOR_ID_ADI
#define PCI_DEVICE_ID	PCI_DEVICE_ID_ADSP21535
#define PCI_CLASS		PCI_CLASS_SP_OTHER	/* other signal proc */
#define PCI_REVISION_ID	0x0	/* board rev */
#define PCI_MIN_GRANT	0x1	/* = 0.25 usecs for 8 DWord FIFO */
#define PCI_MAX_LATENCY	0x2	/* = 0.50 usecs for 32-byte PCI read (16 PCI clks) */

// PCI_IO_SIZE & PCI_MEM_SIZE are defined in VisualDSP\Blackfin\include\defBF535.h

// #define PCI_IO_SIZE	256	/* max window size to match host */
#define PCI_IO_BARMASK	(~(PCI_IO_SIZE-1))
// #define PCI_MEM_SIZE	0x40000	/* 256 KB to match host */ 
#define PCI_MEM_BARMASK (~(PCI_MEM_SIZE-1))
//#define PCI_MEM_BARMASK	0xFFFC0000	
/*****************************************************************/
#endif	/* _PCI_IDS_H_ */