opcodes.lst

中断列表(4) 712K

CPU:  I486 +
Type of Instruction: System

Instruction: INVD

Description:

	     FLUSH INTERNAL CACHE
   ( It means that all lines of internal caches sets as
    invalid )
	 SIGNAL EXTERNAL CACHE TO FLUSH

Notes: This instruction not work in Real Mode and  in
Protected mode work only in ring 0 ;

Flags Affected: None

CPU mode: PM0,SMM?

Physical Form:		 INVD
COP (Code of Operation): 0FH 08H
Clocks: Cyrix Cx486SLC : 4
	      i486     : 4
	      Pentium  : 15

----------O-INVLPG---------------------------------
OPCODE INVLPG  - Invalidate Page Entry In TLB

CPU:  I486 +
Type of Instruction: System

Instruction: INVLPG mem

Description:

	IF found in data or code (if both) (or common if single)
	   TLB entry with linear address (page part) same as
	   memory operand <mem> then mark this entry as Invalid;

Notes: This instruction not work in Real Mode and  in
Protected mode work only in ring 0 ;

Flags Affected: None

CPU mode: RM,PM,VM,SMM

Physical Form:		 INVLPG mem
COP (Code of Operation): 0FH 01H mm111mmm
Clocks: Cyrix Cx486SLC : 4
	      i486     : 12 if hit
		       : 11 if not hit
	      Pentium  : 25

----------O-JMPX-----------------------------------
OPCODE JMPX  - Jump and change to 64-bit ISA.

CPU:  Merced
Type of Instruction: User

Instruction: JMPX	dest

Description:

	This instruction make jump to specified address, and
	change execution mode from IA-32 to IA-64.
	So address must be 16-byte aligned.

Note:	The other method to cnange execution mode to IA-64 is interrupt
	to 64-bit code or IRET in IA-32 routine, which will be called from
	IA-64.

Flags Affected: None

CPU mode: IA-32

Physical Form:		 JMPX	rel16/rel32
			 JMPX	r/m16
			 JMPX	r/m32
COP (Code of Operation): ???
Clocks:		Merced :

----------O-LOADALL--------------------------------
OPCODE LOADALL	- Load All Registers

CPU:  Intel 386+ +all clones
Type of Instruction: System
		    (Work only then CPL=0)

Instruction: LOADALL

Description:
	      Load All Registers (Include Shadow Registers) from Table
	      Which Begin on  place pointed ES:EDI

Format of LOADALL Table:
	(Table )
	       Offset  Len  Description
		0H	4	CR0
		4H	4	EFLAGS
		8H	4	EIP
		CH	4	EDI
		10H	4	ESI
		14H	4	EBP
		18H	4	ESP
		1CH	4	EBX
		20H	4	EDX
		24H	4	ESX
		28H	4	EAX
		2CH	4	DR6
		30H	4	DR7
		34H	4	TR	 (16 bit, zero filled up)
		38H	4	LDT  ---------
		3CH	4	GS   ---------
		40H	4	FS   ---------
		44H	4	DS   ---------
		48H	4	SS   ---------
		4CH	4	CS   ---------
		50H	4	ES   ---------
		54H	4	TSS.attrib
		58H	4	TSS.base
		5CH	4	TSS.limit
		60H	4	0s
		64H	4	IDT.base
		68H	4	IDT.limit
		6CH	4	0s
		70H	4	GDT.base
		74H	4	GDT.limit
		78H	4	LDT.attrib
		7CH	4	LDT.base
		80H	4	LDT.limit
		84H	4	GS.attrib
		88H	4	GS.base
		8CH	4	GS.limit
		90H	4	FS.attrib
		94H	4	FS.base
		98H	4	FS.limit
		9CH	4	DS.attrib
		A0H	4	DS.base
		A4H	4	DS.limit
		A8H	4	SS.attrib
		ACH	4	SS.base
		B0H	4	SS.limit
		B4H	4	CS.attrib
		B8H	4	CS.base
		BCH	4	CS.limit
		C0H	4	ES.attrib
		C4H	4	ES.base
		C8H	4	ES.limit
		CCH	4	Length of table
		D0H	30h	Unused,not loaded
		100H	4	Temporary Register IST
		104H	4	Temporary Register I
		108H	4	Temporary Register H
		10CH	4	Temporary Register G
		110H	4	Temporary Register F
		114H	4	Temporary Register E
		118H	4	Temporary Register D
		11CH	4	Temporary Register C
		120H	4	Temporary Register B
		124H	4	Temporary Register A

Format	of Attrib field:

	       Byte	Description
	       0	0s
	       1	AR (Access Right) byte in the Descriptor format
			Note:
			   P bit is a valid bit
			   if valid bit=0 then Shadow Register is invalid and
			      INT 0DH - General Protection Fault call
			   DPL of SS,CS det. CPL
	       2-3	0s

Flags Affected: All (FLAGS Register Reload)

CPU mode: RM,PM0

Physical Form:		 LOADALL
COP (Code of Operation): 0FH 07H
Clocks:	      i386XX   : n/a
	      i486XX   : n/a

Note: This operation used 102 data transfer cycles on 32bit bus
      Typical clocks:
	      i386SX: ~350
	      i386DX: ~290
	      i486XX: ~220

----------O-LOADALL--------------------------------
OPCODE LOADALL	- Load All Registers From Table

CPU:  Intel 80286 and all its clones
Type of Instruction: System
		    (Work only then CPL=0)

Instruction: LOADALL

Description:
	      Load All Registers (Include Shadow Registers) from Table
	      Which Begin on  000800H  Address, Len of this table is
	      66H

Format of LOADALL Table:
	(Table )
	       Address	Len  Description
		800H	6	None
		806H	2	MSW
		808H	14	None
		816H	2	TR
		818H	2	FLAGS
		81AH	2	IP
		81CH	2	LDTR
		81EH	2	DS
		820H	2	SS
		822H	2	CS
		824H	2	ES
		826H	2	DI
		828H	2	SI
		82AH	2	BP
		82CH	2	SP
		82EH	2	BX
		830H	2	DX
		832H	2	CX
		834H	2	AX
		836H	6	ES Shadow Descriptor
		83CH	6	CS Shadow Descriptor
		842H	6	SS Shadow Descriptor
		848H	6	DS Shadow Descriptor
		84EH	6	GDTR
		854H	6	LDT Shadow Descriptor
		85AH	6	IDTR
		860H	6	TSS Shadow Descriptor

Format	of Shadow Descriptor:

	       Byte	Description
	       0-2	24bit Phisical Address
		3	AR (Access Right) byte
	       4-5	16bit Segment Limit

Format	of GDTR and IDTR:

	       Byte	Description
	       0-2	24bit Phisical Address
		3	0s
	       4-5	16bit Segment Limit

Note: Using this instruction we may turn on "Big Real Mode" i.e. mode then
PG=1,PE=0,cpl=0. This mode very usefull,But Pentium never  support this
instruction.

Flags Affected: All (FLAGS Register Reload)

CPU mode: RM,PM0

Physical Form:		 LOADALL
COP (Code of Operation): 0FH 05H
Clocks:	      80286    : 195

----------O-MOVD-----------------------------------
OPCODE MOVD   -	 Move Dwords

CPU:  all which supported IA MMX:
      Pentium (P55C only), Pentium (tm) Pro  (P6) future models
Type of Instruction: User

Instruction: MOVD  dest,src

Description:

	IF dest is MMi register THEN
	{
		dest[63..32] <- 0
		dest[31..0]  <- src
	} ELSE	  ; If dest is DWORD
	dest <- src [31..0]

Note: This instruction moved DWORDs to/from MMX registers

Flags affected:	 None

Exceptions:

RM	PM	VM	SMM	Description
	#GP(0)			If result in Non-Writable segment
	#GP(0)			If Illegal memory operand's EA in CS,DS,ES,FS,GS
	#SS(0)			If illegal memory operand's EA in SS
	  #PF(fcode)		If page fault
	#AC	#AC		If unaligned memory reference then alignment
				check enabled and in ring 3.
#UD	#UD	#UD	#UD	If CR0.EM = 1
#NM	#NM	#NM	#NM	If CR0.TS = 1
#MF	#MF	#MF	#MF	If pending FPU Exception

++++++++++++++++++++++++++++++++++++++
COP & Times:

MOVD	mm,r/m32	0FH 6EH	PostByte
MOVD	r/m32,mm	0Fh 7Eh	PostByte

			mm,r/m32   r/m32,mm
     P55C:	n/a	(~1)	   (~1)
future P6:	n/a	(~1)	   (~1)

----------O-MOVQ-----------------------------------
OPCODE MOVQ   -	 Move Qwords

CPU:  all which supported IA MMX:
      Pentium (P55C only), Pentium (tm) Pro  (P6) future models
Type of Instruction: User

Instruction: MOVQ  dest,src

Description:

	dest <- src

Note: This instruction moved QWORDs to/from MMX registers
      Of course, IA support Big-endian QWORDS.

Flags affected:	 None

Exceptions:

RM	PM	VM	SMM	Description
	#GP(0)			If result in Non-Writable segment
	#GP(0)			If Illegal memory operand's EA in CS,DS,ES,FS,GS
	#SS(0)			If illegal memory operand's EA in SS
	  #PF(fcode)		If page fault
	#AC	#AC		If unaligned memory reference then alignment
				check enabled and in ring 3.
#UD	#UD	#UD	#UD	If CR0.EM = 1
#NM	#NM	#NM	#NM	If CR0.TS = 1
#MF	#MF	#MF	#MF	If pending FPU Exception

++++++++++++++++++++++++++++++++++++++
COP & Times:

MOVQ	mm,mm/m64	0FH 6FH	PostByte
MOVQ	mm/m64,mm	0Fh 7Fh	PostByte

Note: In PostByte instead IU registers used MMX registers,
      0Fh 6Fh C0h means	 MOVQ  MM0,MM0

			mm,r/m32   r/m32,mm
     P55C:	n/a	(~1)	   (~1)
future P6:	n/a	(~1)	   (~1)

----------O-MOVSPA---------------------------------
OPCODE MOVSPA	 -  Move Stack Pointer After Bank Switched

CPU:  NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
Type of Instruction: System

Instruction:  MOVSPA

Description:  This instruction transfer	 both SS and SP	 of the old register
	      bank to new register bank after the bank has been switched by
	      interrupt or BRKCS instruction.

Flags Affected:	 None

CPU mode: RM

+++++++++++++++++++++++
Physical Form:	MOVSPA
COP (Code of Operation)	 : 0Fh 25h

Clocks:	 16

----------O-MOVSPB---------------------------------
OPCODE MOVSPB	 -  Move Stack Pointer Before Bamk Switching

CPU:  NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
Type of Instruction: System

Instruction:  MOVSPB  Number_of_bank

Description:  The MOVSPB instruction transfers the current SP and SS before
	      the bank switching to new register bank.

Note:	      New Register Bank Number indicated by lower 3bit of Number_of_
	      _bank.

Note:	      See BRKCS instruction for more info about banks.

Flags Affected:	 None

CPU mode: RM

+++++++++++++++++++++++
Physical Form:	MOVSPB	  reg16
COP (Code of Operation)	 : 0Fh 95h <1111 1RRR>

Clocks:	 11

----------O-NOT1-----------------------------------
OPCODE NOT1  -	Invert a Specified bit

CPU: NEC/Sony  all  V-series
Type of Instruction: User

Instruction:  NOT1 dest,bitnumb

Description:

		(BIT bitnumb OF dest) <-  NOT (BIT bitnumb OF dest);

Flags Affected: None

CPU mode: RM

+++++++++++++++++++++++
Physical Form:		   NOT1 reg/mem8,CL
COP (Code of Operation)	 : 0FH 16H  Postbyte

Physical Form:		   NOT1 reg/mem8,imm8
COP (Code of Operation)	 : 0FH 1EH  Postbyte imm8

Physical Form:		   NOT1 reg/mem16,CL
COP (Code of Operation)	 : 0FH 17H  Postbyte

Physical Form:		   NOT1 reg/mem16,imm8
COP (Code of Operation)	 : 0FH 1FH  Postbyte  imm8

Clocks:				 NOT1
	     r/m8,CL	r/m8,i8		r/m16,CL   r/m16,i8
NEC V20:      4/18	 5/19		  4/18	     5/19

----------O-OIO-----------------------------------
OPCODE OIO  -  Official Undefined Opcode

CPU:	Cyrix Cx6x86 (same code on AMD Am5k86)

Logical Form:	OIO

Description:
		Caused #UD exception

Flags Affected: No Flags Affected
CPU Mode : RM,PM,VM,VME,SMM

Exceptions :
	RM	PM	V86	VME	SMM
	#UD	#UD	#UD	#UD	#UD Undefined Instruction
	No more Exceptions

Note :
	This instruction caused #UD. AMD  guaranteed that in future AMD's
	CPUs this instruction will caused #UD. Of course all previous CPUs
	(186+) caused #UD on this opcode. This instruction used by software
	writers for testing #UD exception servise routine.

++++++++++++++++++++++++++++++

Physical Form : UD

COP (Code of Operation) : 0Fh FFh

Clocks :	UD
8088:	Not supported
NEC V20:	Not supported
80186:	~int
80286:	~int
80386:	~int
Cx486SLC:	~int
i486:	~int
Cx486DX:	~int
Cx5x86:		~int
Pentium:	~int
Nx5x86:		~int
Cx6x86:		~int
Am5k86:		~int
Pentium Pro:	~int

++++++++++++++++++++++++++++++

----------O-PACKSSDW-------------------------------
OPCODE PACKSSDW	  -  Pack with Signed Saturation dword to word

CPU:  all which supported IA MMX:
      Pentium (P55C only), Pentium (tm) Pro  (P6) future models
Type of Instruction: User

Instruction: PACKSSDW  dest,src

Description:

	dest[15..0]	<-	SaturateSignedDWordToSignedWord dest[31..0]
	dest[31..16]	<-	SaturateSignedDWordToSignedWord dest[63..32]
	dest[47..32]	<-	SaturateSignedDWordToSignedWord src[31..0]
	dest[63..46]	<-	SaturateSignedDWordToSignedWord src[63..32]

Note: This instruction packs and saturates signed data from src and dest to
      dest.
      If signed value of word larger or smaller that the range of signed byte
      value is saturated (in case of overflow to 7Fh, in underflow to 80h).

Flags affected:	 None

Exceptions:

RM	PM	VM	SMM	Description
	#GP(0)			If Illegal memory operand's EA in CS,DS,ES,FS,GS
	#SS(0)			If illegal memory operand's EA in SS
	  #PF(fcode)		If page fault
	#AC	#AC		If unaligned memory reference then alignment
				check enabled and in ring 3.
#UD	#UD	#UD	#UD	If CR0.EM = 1
#NM	#NM	#NM	#NM	If CR0.TS = 1
#MF	#MF	#MF	#MF	If pending FPU Exception

++++++++++++++++++++++++++++++++++++++
COP & Times:

PACKSSDW mm,mm/m64	0FH 6BH	PostByte

     P55C:	n/a
future P6:	n/a

----------O-PACKSSWB-------------------------------
OPCODE PACKSSWB	  -  Pack with Signed Saturation word to Byte

CPU:  all which supported IA MMX:
      Pentium (P55C only), Pentium (tm) Pro  (P6) future models
Type of Instruction: User

Instruction: PACKSSWB  dest,src

Description:

	dest[7..0]	<-	SaturateSignedWordToSignedByte dest[15..0]
	dest[15..8]	<-	SaturateSignedWordToSignedByte dest[31..16]
	dest[23..16]	<-	SaturateSignedWordToSignedByte dest[47..32]
	dest[31..24]	<-	SaturateSignedWordToSignedByte dest[63..48]
	dest[39..32]	<-	SaturateSignedWordToSignedByte src[15..0]
	dest[47..40]	<-	SaturateSignedWordToSignedByte src[31..16]
	dest[55..48]	<-	SaturateSignedWordToSignedByte src[47..32]
	dest[63..56]	<-	SaturateSignedWordToSignedByte src[63..48]

Note: This instruction packs and saturates signed data from src and dest to
      dest

Flags affected:	 None

Exceptions:

RM	PM	VM	SMM	Description
	#GP(0)			If Ill