📄 opcodes.lst
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OPCODE BTCLR - Bit Test, If it True Clear and Branch
CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
Type of Instruction: User
Instruction: BTCLR var,bitnumber,Short_Label
Description:
IF BIT(bitnumber OF var) =1 THEN
{
PC <- PC + ext - disp8;
BIT(bitnumber OF var) <-0
}
Flags Affected: None
CPU mode: RM
+++++++++++++++++++++++
Physical Form: BTCLR reg/mem8,imm3, short_label
COP (Code of Operation) : 0Fh 9Ch PostByte imm3 Short_Label (Total=5 bytes)
Clocks: 29
----------O-CALLN----------------------------------
OPCODE CALLN - Call Native Mode Routine
CPU: NEC/Sony V20/V30 etc
Type of Instruction: System
Instruction: CALLN intnum
Description:
CALLN instruction call (interrupt service in Native Mode)
from 8080 emulation mode:
PUSH FLAGS
PUSH CS
PUSH IP
IF <- 0
TF <- 0
MD <- 1
MOV CS,0:[intnum*4+2]
MOV IP,0:[intnum*4]
Flags Affected: IF,TF,MD
CPU mode: 8080 Emulation
+++++++++++++++++++++++
Physical Form: CALLN imm8
COP (Code of Operation) : EDH EDH imm8
Clocks:
NEC V20/V30: 38-58
----------O-CLEAR1---------------------------------
OPCODE CLEAR1 - Clear one bit
CPU: NEC/Sony all V-series.
Type of Instruction: User
Instruction: CLEAR1 dest,bitnumb
Description:
BIT bitnumb OF dest <- 0;
Flags Affected: None
CPU mode: RM
+++++++++++++++++++++++
Physical Form: CLEAR1 reg/mem8,CL
COP (Code of Operation) : 0FH 12H Postbyte
Physical Form: CLEAR1 reg/mem8,imm8
COP (Code of Operation) : 0FH 1AH Postbyte imm8
Physical Form: CLEAR1 reg/mem16,CL
COP (Code of Operation) : 0FH 13H Postbyte
Physical Form: CLEAR1 reg/mem16,imm8
COP (Code of Operation) : 0FH 1BH Postbyte imm8
Clocks: CLEAR1
r/m8,CL r/m8,i8 r/m16,CL r/m16,i8
NEC V20: 5/14 6/15 5/14 6/15
----------O-CMOVcc---------------------------------
OPCODE CMOVcc - Conditional Move
CPU: P6
Type of Instruction: User
Instruction: CMOVcc dest,sorc
Description:
IF condition(cc) is true THEN dest <- sorc;
Flags Affected: None
CPU mode: RM,PM,VM,SMM
+++++++++++++++++++++++
Physical Form & COPs:
CMOVO reg,reg/mem 0FH 40H Postbyte
CMOVNO reg,reg/mem 0FH 41H Postbyte
CMOVC reg,reg/mem 0FH 42H Postbyte
CMOVNC reg,reg/mem 0FH 43H Postbyte
CMOVZ reg,reg/mem 0FH 44H Postbyte
CMOVNZ reg,reg/mem 0FH 45H Postbyte
CMOVNA reg,reg/mem 0FH 46H Postbyte
CMOVA reg,reg/mem 0FH 47H Postbyte
CMOVS reg,reg/mem 0FH 48H Postbyte
CMOVNS reg,reg/mem 0FH 49H Postbyte
CMOVP reg,reg/mem 0FH 4AH Postbyte
CMOVNP reg,reg/mem 0FH 4BH Postbyte
CMOVL reg,reg/mem 0FH 4CH Postbyte
CMOVNL reg,reg/mem 0FH 4DH Postbyte
CMOVNG reg,reg/mem 0FH 4EH Postbyte
CMOVG reg,reg/mem 0FH 4FH Postbyte
Clocks: ~1 (~pairing with other instructions)
----------O-CMP4S----------------------------------
OPCODE CMP4S - Compare for packed BCD strings
CPU: NEC/Sony all V-series
Type of Instruction: User
Instruction: CMP4S
Description:
SetFlaGS( BCD STRING (ADDRESS=ES:DI,LENGTH=CL) -
BCD STRING (ADDRESS=DS:SI,LENGTH=CL) );
Note: si,di, other registers not changed
Flags Affected: OF,CF,ZF
;; ZF set if RESULT of subtraction is zero.
;; CF,OF set as result of operation with most
;; signification BCDs.
CPU mode: RM
+++++++++++++++++++++++
Physical Form: CMP4S
COP (Code of Operation) : 0FH 26H
Clocks: CMP4S
NEC V20: ~7+19*CL
----------O-CMPXCHG8B------------------------------
OPCODE CMPXCHG8B - Compare and exchange 8 bytes
CPU: Pentium (tm), Pentium Pro(tm), AMD Am5k86
Type of Instruction: Operation
Instruction: CMPXCHG8B dest
Note: dest is memory operand: QWORD PTR [memory]
Description:
IF ( QWORD(EDX:EAX) = dest) THEN
{
ZF <- 1;
dest <- QWORD(ECX:EBX);
}
ELSE
{
ZF <- 0;
EDX:EAX <- dest
}
END
Flags Affected: ZF
CPU mode: RM,PM,VM,SMM
Physical Form: CMPXCHG8B mem64
COP (Code of Operation) : 0FH C7H Postbyte
Clocks: Pentium : 10
Note: Postbyte MMRRRMMM: MM<>11 if (==) then INT 6
----------O-CMPXCHG--------------------------------
OPCODE CMPXCHG - Compare and exchange
CPU: i486+
Type of Instruction: User
Instruction: CMPXCHG dest,sorc
Description:
Acc = if OperationSize(8) -> AL
OperationSize(16) -> AX
OperationSize(32) -> EAX
IF ( Acc = dest) THEN
{
ZF <- 1;
dest <- sorc;
}
ELSE
{
ZF <- 0;
Acc <- dest;
}
END
Note: This instruction used to support semaphores
Flags Affected: ZF ( see description)
OF,SF,AF,PF,CF ( like CMP instruction ) ( see description)
CPU mode: RM,PM,VM,SMM
+++++++++++++++++++++++
Physical Form: CMPXCHG r/m8,r8
COP (Code of Operation) : 0FH A6H Postbyte ; i486 (A-B0 step)
: 0FH B0H Postbyte ; i486 (B1+ step clones
; and upgrades)
Clocks:
Intel i486 : 6/7 if compare OK
: 6/10 if compare FAIL
Cyrix Cx486SLC : 5/7
Pentium (tm) : 6
Penalty if cache miss :
Intel i486 : 2
Cyrix Cx486SLC : 1
+++++++++++++++++++++
Physical Form: CMPXCHG r/m16,r16
CMPXCHG r/m32,r32
COP (Code of Operation) : 0FH A7H Postbyte ; i486 (A-B0 step)
: 0FH B1H Postbyte ; i486 (B1+ step clones
; and upgrades)
Clocks:
Intel i486 : 6/7 if compare OK
: 6/10 if compare FAIL
Cyrix Cx486SLC : 5/7
Pentium (tm) : 6
Penalty if cache miss :
Intel i486 : 2
Cyrix Cx486SLC : 1
----------O-CPUID----------------------------------
OPCODE CPUID - CPU Identification
CPU: Intel 486DX/SX/DX2 SL Enhanced and all later
Intel processors include ( IntelDX4, IntelSX2,
Pentium etc.), UMC microprocessors: U5S,U5SD,U5S-VL.
Cyrix M1, AMD K5, Intel P6, and AMD Ehnanced Am486 CPU,
such as A80486DX4-100SV8B.
Note: i.e. 1993+ years processors produced by Intel
Note: To know if your CPU support CPUID instruction
try to set ID flag ( bit 21 of EFLAGS ) to 1, and
if it sets this mean that CPUID support.(Soft).
Or If Your CPU is Intel Look for '&E' signature on
Top side of Chip.(Hard)
Type of Instruction: Operation
Instruction: CPUID
Description:
IF (EAX=0) THEN // All
{
EAX <- Maximum value of EAX to CALL CPUID instruction
1 for all processors (date 1 September 1994)
may be >1 in future microprocessors
;; EBX,EDX and ECX contain a OEM name string
;; for Intel this string is 'GenuineIntel'
EBX <- 756E6547H i.e. 'Genu'
EDX <- 49656E69H i.e. 'ineI'
ECX <- 6C65746EH i.e. 'ntel'
;; for UMC this string is 'UMC UMC UMC '
EBX <- 20434D55H i.e. 'UMC '
EDX <- 20434D55H i.e. 'UMC '
ECX <- 20434D55H i.e. 'UMC '
;; for Cyrix this string is 'CyrixInstead' (Cx6x86,Cx5x86 steps B+)
;; for AMD this string is 'AuthenticAMD' (K6,K5,486 Enhanced CPUs)
;; for last NexGen is 'NexGenDriven' (Nx5x86 latest models)
;; for Centaur Technology is 'CentaurHauls' (IDT)
}
ELSEIF (EAX=1) THEN // All
{
EAX[3:0] <- Stepping ID
EAX[7:4] <- Model
EAX[11:8] <- Family
; 3 - 386 family
; 4 - i486 family
; 5 - Pentium family
; 6 - Pentium Pro family
EAX[15:12] <- Reserved
; 0 - Original OEM processor
; 1 - OverDrive
; 2 - Dual Processor
Note: Pentium P54C have pin CPUTYPE which
define is this CPU First or Second e.t.c
in System.
So, if this chip set in "First" socket it
return for example 0425h, but THIS chip
return 2425h if we insert it in "Second"
socket.
Note: Refer to Appendix B for more information.
EAX[31:16] <- Reserved and set to 0s now
EDX <- Compability flags
;; below all info if bit flag =1
EDX[0] <- FPU: FPU on Chip
EDX[1] <- VME: Virtual Mode Extention present
EDX[2] <- DE: Debbuging Extentions
EDX[3] <- PSE: CPU support 4MB size pages
EDX[4] <- TSC: TSC present (See RDTSC command)
EDX[5] <- MSR: CPU have Pentium Compatible MSRs
EDX[6] <- PAE: Physical Address Extension (Intel)
EDX[6] <- PTE: Support PTE (Cyrix)
When set in PTE TLB will not be flushed
when CR3 is written.
EDX[7] <- MCE: Machine Check exception
EDX[8] <- CX8: Support CMPXCHG8B instruction
EDX[9] <- APIC: Local APIC on Chip (Intel)
PGE: Page Global Extension (K5)
EDX[10]<- reserved
EDX[11]<- SEP: Fast System Call feature (Pentium Pro)
EDX[12]<- MTRR: CPU support Memory Type Range Register (MTRR)
EDX[13]<- PGE: Page Global Feature support
EDX[14]<- MCA: Machine Check Architecture
EDX[15]<- CMOV: CPU support CMOV instruction
EDX[16]<- PAT: Page Attribute Table
EDX[22..16] <- Reserved
EDX[23] <- MMX: CPU support IA MMX
EDX[24] <- FXSR: CPU Support Fast Save/Restore (IA MMX-2)
EDX[31:25] <- Reserved and set to 0s now
}
ELSEIF (EAX=2)
{
AL = 1 (Pentium Pro, Pentium II)
remainder of EAX and EBX,ECX,EDX contain bytes which
described cache architecture on this chip.
Description of this bytes is:
Value Description
00h None
01h Instruction TLB, 4K page, 4way, 64 entry
02h Instruction TLB, 4M page, 4way, 4 entry
03h Data TLB, 4K page, 4way, 64 entry
04h Data TLB, 4M page, 4way, 8 entry
06h Instruction Cache, 8K, 4 way, 32 byte per line
0Ah Data cache, 8K, 2 way, 32 byte per line
41h Unifed L2 cache, 32 byte per line, 4 way, 128KB
42h Unifed L2 cache, 32 byte per line, 4 way, 256KB
43h Unifed L2 cache, 32 byte per line, 4 way, 512KB
44h Unifed L2 cache, 32 byte per line, 4 way, 1MB
45h Unifed L2 cache, 32 byte per line, 4 way, 2MB
(Cyrix MediaGX MMX Enhanced)
70h TLB 32-bit entry, 4 way, 4K cache
80h L1 cache 4-way associative, 16byte/line
}
ELSEIF (EAX = 80000000h) // (K5 not SSA/5),K6, Cyrix GXm
{
EBX,ECX,EDX <- Undefined
EAX <- Largest Extended function value recognized by CPUID.
(Note: Extended CPUID functions started with 80000000h)
(Example: For AMD 5k86 (K5) = 80000005h )
}
ELSEIF (EAX = 80000001h) // K5,K6,Cyrix GXm
{
EAX <- AMD Processor Signature
0000051Xh - for AMD 5k86 (K5 not SSA/5)
0000066Xh - for AMD 6k86 (K6)
EBX,ECX <- Undefined
EDX <- Extended Feature Flags
EDX[0] <- FPU: FPU on Chip
EDX[1] <- VME: Virtual Mode Extention present
EDX[2] <- DE: Debbuging Extentions
EDX[3] <- PSE: CPU support 4MB size pages
EDX[4] <- TSC: TSC present (See RDTSC command)
EDX[5] <- MSR: CPU have K5 Compatible MSRs
EDX[6] <- 0 (Reserved)
EDX[7] <- MCE: Machine Check exception
EDX[8] <- CX8: Support CMPXCHG8B instruction
EDX[9] <- Reserved
EDX[10]<- Support SYSCALL and SYSRET instruction (!!!)
EDX[11,12]<- reserved
EDX[13]<- PGE: Page Global Feature support
EDX[14]<- reserved
EDX[15]<- CMOV: CPU support CMOV instruction
EDX[16]<- FCMOV: CPU support FP. FCMOV (!!!)
EDX[22..16] <- Reserved
EDX[23] <- MMX: CPU support IA MMX
EDX[24] <- (Cyrix) Cyrix Extended MMX
EDX[30..24] <- Reserved
EDX[31] <- AMD 3D support
;Note: For AMD K5 = 000021BFh
For AMD K6 = 008005BFh
}
ELSEIF (EAX = 80000002h,80000003h,80000004h) // AMD K5,K6, Cyrix GXm
{
EAX, EBX, ECX ,EDX = CPU Name
// Note: for AMD K5 (Don't forget x86 is BIG-Endian!!)
// CPUID(EAX) EAX EBX ECX EDX
// 80000002h 2D444D41 7428354B 5020296D 65636F72
// AMD- K5(r m) P roce
// 80000003h 726F7373 00000000 00000000 00000000
// ssor
// 80000004h 00000000 00000000 00000000 00000000
}
ELSEIF (EAX = 80000005h) // AMD K5,K6
{ // TLB and Cache information
EAX <- Reserved
EBX <- TLB Information:
EBX[31..24] <- Data TLB: Associativity
(if Full assocuiativity = FFh)
EBX[23..16] <- Data TLB: Number of Entryes
EBX[15..8] <- Instruction TLB: Associativity
(if Full assocuiativity = FFh)
EBX[7..0] <- Instruction TLB: Number of Entryes
ECX <- L1 Data Cache Information
ECX[31..24] <- Size in KB
ECX[23..16] <- Associativity (if full = FFh)
ECX[15..8] <- Lines per Tag
ECX[7..0] <- Line size in Bytes
EDX <- L1 Instruction Cache Information
ECX[31..24] <- Size in KB
ECX[23..16] <- Associativity (if full = FFh)
ECX[15..8] <- Lines per Tag
ECX[7..0] <- Line size in Bytes
// Note: after execution CPUID with EAX = 80000005h
// reg AMD K5 AMD K6
// EBX 04800000 02800140
// ECX 08040120 20020220
// EDX 10040120 20020220
}
ELSE THEN
{
EAX,EBX,ECX,EDX <- Undefined
}
END.
Refer to: Appendix B for more informations about CPU codes.
Note: On IDT C6 CPU we may set any Identification string and family/model/
stepping info. (See MSRs 108h,109h for More Details).
Here is 3 examples of Information we can may get from CPUID instruction:
1) UMC U5S
Note: All UMC Chips: U5S,U5SD, 3V chips never have FPU on-chip,
and never support VME
Maximum Available of CPUID info entrys:1
Vendor string is : "UMC UMC UMC "
Model Info :
Stepping ID is : 3
Model : 2
Family : 4
M field : 0
Compability Flags:
FPU on Chip :-
Virtual Mode Extensions present :-
CPU support I/O breakpoints :-
CPU support 4MB pages :-
Time Stamp Counter Presents :-
CPU have Pentium compatible MSRs :-
Machine Check Exception Presents :-
CMPXCHG8B instruction support :-
APIC on Chip :-
2) Intel 486
Note: All SL Enhanced 486: { i486SX,i486DX,i486DX2 marked '&E' on chip
surface }, IntelSX2,IntelDX4 support VME !!!!
But: Sxs never have FPU on chip.
Maximum Available of CPUID info entrys:1
Vendor string is : "GenuineIntel"
Model Info :
Stepping ID is : 0
Model : 8
Family : 4
M field : 0
Compability Flags:
FPU on Chip :+
Virtual Mode Extensions present :+
CPU support I/O breakpoints :-
CPU support 4MB pages :-
Time Stamp Counter Presents :-
CPU have Pentium compatible MSRs :-
Machine Check Exception Presents :-
CMPXCHG8B instruction support :-
APIC on Chip :-
3) Pentium
Note: P54C may say that build-in APIC not present if it
not supported by external hardware !!!!! (This data from
P54C in single processor configuration)
Maximum Available of CPUID info entrys:1
Vendor string is : "GenuineIntel"
Model Info :
Stepping ID is : 1
Model : 2
Family : 5
M field : 0
Compability Flags:
FPU on Chip :+
Virtual Mode Extensions present :+
CPU support I/O breakpoints :+
CPU support 4MB pages :+
Time Stamp Counter Presents :+
CPU have Pentium compatible MSRs :+
Machine Check Exception Presents :+
CMPXCHG8B instruction support :+
APIC on Chip :-
4) Pentium OverDrive
Note: P24T never have Machine Check Exception
Maximum Available of CPUID info entrys:1
Vendor string is : "GenuineIntel"
Model Info :
Stepping ID is : 1
Model : 3
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