opcodes.lst

中断列表(4) 712K

OPCODE LIST			Release 60		Last change 03jan99

------------------  OPCODE.LST	----------------------------
This is DOC 'bout undocument command and document command
of any last processors. And 'bout some registers and
Chips specific stuffs.
 -----------------------------------------------------------
 (C) (P) Potemkin's Hackers Group 1994...1998
 -----------------------------------------------------------
Revision 4.00	PRELIMINARY			27 Sep 1998
 -----------------------------------------------------------
Latest versions available on Web:
	http://www.chat.ru/~phg
Our contact E-mail:
	[e-mail]
ICQ:
	17806489
 ------------------------------------------------------------
[New In revision 3.90]
  o  Update steppings
  o  Update Katmai Info
  o  Some reformating :)
  -----------------------------------------------------------
[New In revision 3.81]
  o  Update steppings
  o  Add Vendor-specified instruction times
  o  Add some new info in appendix G.
  o  Some bugfixes
  -----------------------------------------------------------
[New In revision 3.80]
  o  Cyrix EMMX instructions
  o  AMD 3D instructions
  o  IA-MMX2 codes
  o  News in CPUID
  o  Update Steppings
  ------------------------------------------------------------
[New In revision 3.51]
  o  Some new Merced Instructions  (IA-32 and IA-64)
  o  Some Katmai instructions (IA MMX-2)
  o  IDT C6 MSRs
  o  News in CPUID
  o  News in CR4
  o  Update Cyrix CPUs Info
  o  New operations codes (AMD-3D,Cyrix EMMX)
  o  More Pentium-II MSRs
  o  Some SMM Info
-------------------------------------------------------------

----------O-AAA------------------------------------
OPCODE AAA   -	ASCII adjust AX after addition

CPU:  8086+
Type of Instruction: User

Instruction:  AAA   ; (no operands)

Description:

	IF ((( AL and 0FH ) > 9 ) or (AF==1)
	THEN {
		IF CPU<286 THEN {  AL <- AL+6 }
			   ELSE {  AX <- AX+6 }
		AH <- AH+1
		CF <- 1
		AF <- 1
	} ELSE {
		CF <- 0
		AF <- 0
	}
	AL <- AL and 0Fh

Note: This istruction incorrectly documented in Intel's materials.
      See description field.

Flags Affected:	AF,CF	    (modified)
		OF,SF,ZF,PF (undefined)

Faults:
	RM	PM	V86	VME
	None

CPU mode: RM,PM,VM,SMM

+++++++++++++++++++++++
Physical Form:
COP (Code of Operation)	 : 37H

Clocks:
		AAA
8086:		4
8088:		4
80186:		8
80286:		3
80386:		4
i486:		3
Pentium:	3

Cx486SLC:	4
Cx486DX:	4
IBM 486BL3X:	4
UMC U5S:	1

----------O-AAD------------------------------------
OPCODE AAD    - ASCII adjust AX before Division

CPU:  8086+
Type of Instruction: User

Instruction:  AAD basen

Description:
		AL <- (AH*basen) + AL
		AH <- 0

Flags Affected: SF,ZF,PF	(modified)
		OF,AF,CF	(undefined)

Faults:
	RM	PM	V86	VME	SMM
	None

CPU mode: RM,PM,VM,SMM

Note:	AAD	without operands means AAD with operand 0AH.

Note: NECs understand only AAD 0AH form.

+++++++++++++++++++++++

Physical Form: AAD imm8

COP (Code of Operation)	 : D5H	imm8

Clocks:		AAD 0AH
8086:		60
80186:		15
80286:		14
80386:		19
i486:		14
Pentium:	10

Cx486SLC:	4
Cx486DX:	4

IBM 486BL3X:	15
UMC	U5S:	11

----------O-AAM------------------------------------
OPCODE AAM    - ASCII adjust AX after Multiply

CPU:  8086+
Type of Instruction: User

Instruction:  AAM basen

Description:
		AH <- AL  / basen
		AL <- AL MOD basen

Flags Affected: SF,ZF,PF	(modified)
		OF,AF,CF	(undefined)

Faults:
	RM	PM	V86	VME	SMM
	None

CPU mode: RM,PM,VM,SMM

Note:	AAM	without operands means AAM with operand 0AH.

WARNING: NECs understand only AAM 0Ah form.

+++++++++++++++++++++++

Physical Form: AAM imm8

COP (Code of Operation)	 : D4H	imm8

Clocks:		AAM 0AH
8086:		83
80186:		19
80286:		16
80386:		17
i486:		15
Pentium:	18

Cx486SLC:	16
Cx486DX:	16

IBM 486BL3X:	17
UMC	U5S:	12

----------O-ADD4S----------------------------------
OPCODE ADD4S  -	 Addition for packed BCD strings

CPU: all NECs  V-series
Type of Instruction: User

Instruction:  ADD4S

Description:

	BCD STRING (ADDRESS=ES:DI,LENGTH=CL) <-
	  BCD STRING (ADDRESS=DS:SI,LENGTH=CL) +
	  BCD STRING (ADDRESS=ES:DI,LENGTH=CL);

Note:	si,di, other registers not changed

Flags Affected: OF,CF,ZF
	;;  ZF set if both strings are zeros.
	;;  CF,OF set as result of operation with most
	;;  signification BCDs.

CPU mode: RM

+++++++++++++++++++++++
Physical Form: ADD4S
COP (Code of Operation)	 : 0FH 20H

Clocks:		ADD4S
NEC V20:	~19*(CL/2)+7

----------O-BOUND----------------------------------
OPCODE BOUND   -  Chack Array Index Against Bounds

CPU:  80186+,NECs
Type of Instruction: User - HLL support

Instruction:  BOUND index,bound_array

Description:

	    IF (index < (opsize ptr [bound_array]))
	       OR
	       (index > (opsize ptr [bound_array+opsize]))
	    THEN  INT 5;

Flags Affected: No Flags Affected

CPU mode: RM,PM,VM,SMM

Faults:
	RM	PM	V86	VME	SMM
		#GP(0)				if result is nonwritable seg.
		#GP(0)				illegal memory operand
						in CS..GS (exc. SS)
		#SS(0)				illegal memory operand in SS
		#PF	#PF
	#UD	#UD	#UD			if 2nd operand is register
	#13					if any part of operand lie
						outside of 0..FFFFh
		#AC	#AC			if CPL=3 and enable AC.

Note:	 (186s&NECs) saved CS:IP BOUND interrupt as pointer to following
      instruction that self.
	 (286+) saved as pointer to BOUND instruction.

+++++++++++++++++++++++

Physical Form: BOUND reg16,mem32
	       BOUND reg32,mem64

COP (Code of Operation)	 : 62H	Postbyte
Note: for 32bit op. add Pfix 66h if in 16bit mode

Clocks:		BOUND reg16,mem16
		In Range	Out Range
80186:				33-35
80286:		13		int+13
80386:		10
i486:		7
Pentium:	8		int+32

Cx486SLC:	11		int+11
Cx486DX:	11		int+11

----------O-BRKCS----------------------------------
OPCODE BRKCS  -	 Break with Contex Switch

CPU:  NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
Type of Instruction: System

Instruction:  BRKCS  bank

Description:

	Perform a High-Speed Software Interrupt with contex-switch to
	register bank indicated by the lower 3-bits of 'bank'.

Info:	NEC V25/V35/V25 Plus/V35 Plus Bank System

	This Chips have	 8 32bytes register banks, which placed in
	Internal chip RAM by addresses:
	xxE00h..xxE1Fh Bank 0
	xxE20h..xxE3Fh Bank 1
	   .........
	xxEC0h..xxEDFh Bank 6
	xxEE0h..xxEFFh Bank 7
	xxF00h..xxFFFh Special Functions Register
	Where xx is Value of IDB register.
	IBD is Byte Register contained Internal data area base
	IBD addresses is FFFFFh and xxFFFh where xx is data in IBD.

	Format of Bank:
	+0	Reserved
	+2	Vector PC
	+4	Save   PSW
	+6	Save   PC
	+8	DS0		;DS
	+A	SS		;SS
	+C	PS		;CS
	+E	DS1		;ES
	+10	IY		;DI
	+11	IX		;SI
	+14	BP		;BP
	+16	SP		;SP
	+18	BW		;BX
	+1A	DW		;DX
	+1C	CW		;CX
	+1E	AW		;AX

	Format of V25 etc. PSW (FLAGS):
	Bit	Description
	15	1
	14	RB2 \
	13	RB1  >	Current Bank Number
	12	RB0 /
	11	V	;OF
	10	DIR	;DF
	9	IE	;IF
	8	BRK	;TF
	7	S	;SF
	6	Z	;ZF
	5	F1	General Purpose user flag #1
			(accessed by Flag Special Function Register)
	4	AC	;AF
	3	F0	General purpose user flag #0
			(accessed by Flag Special Function Register)
	2	P	;PF
	1	BRKI	I/O Trap Enable Flag
	0	CY	;CF

Flags Affected:	 None

CPU mode: RM

+++++++++++++++++++++++
Physical Form:	BRKCS reg16
COP (Code of Operation)	 : 0Fh 2Dh <1111 1RRR>

Clocks:	 15

----------O-BRKEM----------------------------------
OPCODE BRKEM  -	 Break for Emulation

CPU: NEC/Sony V20/V30/V40/V50
Type of Instruction: System

Instruction:  BRKEM  intnum

Description:

		PUSH	FLAGS
		PUSH	CS
		PUSH	IP
		MOV	CS,0:[intnum*4+2]
		MOV	IP,0:[intnum*4]
		MD <- 0;	// Enable 8080 emulation

Note:	BRKEM instruction do software interrupt and then New CS,IP loaded
	it switch to 8080 mode i.e. CPU will execute 8080 code.
	Mapping Table of Registers in 8080 Mode
	8080 Md.   A  B	 C  D  E  H  L	SP PC  F
	native.	   AL CH CL DH DL BH BL BP IP  FLAGS(low)
	For Return of 8080 mode use CALLN instruction.
Note:	I.e. 8080 addressing only 64KB then "Real Address" is CS*16+PC

Flags Affected: MD

CPU mode: RM

+++++++++++++++++++++++
Physical Form:		   BRKEM imm8
COP (Code of Operation)	 : 0FH FFH imm8

Clocks:		BRKEM  imm8
NEC V20:	38

----------O-BRKN-----------------------------------
OPCODE BRKN    -  Break to Native Mode

CPU:  NEC (V25/V35) Software Guard only
Type of Instruction: System

Instruction:  BRKN int_vector

Description:
	     [sp-1,sp-2] <- PSW		; PSW EQU FLAGS
	     [sp-3,sp-4] <- PS		; PS  EQU CS
	     [sp-5,sp-6] <- PC		; PC  EQU IP
	     SP	 <-  SP -6
	     IE	 <-  0
	     BRK <-  0
	     MD	 <-  1
	     PC	 <- [int_vector*4 +0,+1]
	     PS	 <- [int_vector*4 +2,+3]

Note:	The BRKN instruction switches operations in Native Mode
	from Security Mode via Interrupt call. In Normal Mode
	Instruction executed as	 mPD70320/70322 (V25) operation mode.

Flags Affected:	 None

CPU mode: RM

+++++++++++++++++++++++
Physical Form:	BRKN  imm8
COP (Code of Operation)	 : 63h imm8

Clocks:	 56+10T [44+10T]

----------O-BRKS-----------------------------------
OPCODE BRKS    -  Break to Security Mode

CPU:  NEC (V25/V35) Software Guard  only
Type of Instruction: System

Instruction:  BRKS int_vector

Description:
	     [sp-1,sp-2] <- PSW		; PSW EQU FLAGS
	     [sp-3,sp-4] <- PS		; PS  EQU CS
	     [sp-5,sp-6] <- PC		; PC  EQU IP
	     SP	 <-  SP -6
	     IE	 <-  0
	     BRK <-  0
	     MD	 <-  0
	     PC	 <- [int_vector*4 +0,+1]
	     PS	 <- [int_vector*4 +2,+3]

Note:	The BRKS instruction switches operations in Security Mode
	via Interrupt call. In Security Mode the fetched operation
	code is executed after conversion in accordance with build-in
	translation table

Flags Affected:	 None

CPU mode: RM

+++++++++++++++++++++++
Physical Form:	BRKS  imm8
COP (Code of Operation)	 : F1h imm8

Clocks:	 56+10T [44+10T]

----------O-BRKXA----------------------------------
OPCODE BRKXA   -  Break to Expansion Address

CPU:  NEC V33/V53  only
Type of Instruction: System

Instruction:  BRKXA int_vector

Description:
	     [sp-1,sp-2] <- PSW		; PSW EQU FLAGS
	     [sp-3,sp-4] <- PS		; PS  EQU CS
	     [sp-5,sp-6] <- PC		; PC  EQU IP
	     SP	 <-  SP -6
	     IE	 <-  0
	     BRK <-  0
	     MD	 <-  0
	     PC	 <- [int_vector*4 +0,+1]
	     PS	 <- [int_vector*4 +2,+3]
	     Enter Expansion Address Mode.

Note:	In NEC V53 Memory Space dividing into 1024 16K pages.
	The programming model is Same as in Normal mode.

	Mechanism is:
	20 bit Logical Address:	 19..14 Page Num  13..0 Offset

	page Num convertin by internal table to 23..14 Page Base
	tHE pHYSICAL ADDRESS is both Base and Offset.

	Address Expansion Registers:
	logical Address A19..A14	I/O Address
	0				FF00h
	1				FF02h
	...				...
	63				FF7Eh

	Register XAM aliased with port # FF80h indicated current mode
	of operation.
	Format of XAM register (READ ONLY):
	15..1	reserved
	0	XA Flag, if=1 then in XA mode.

Format	of  V53 PSW:
	15..12	1
	11	V
	10	DIR
	9	IE
	8	BRK
	7	S
	6	Z
	5	0
	4	AC
	3	0
	2	P
	1	1
	0	CY

Flags Affected:	 None

CPU mode: RM

+++++++++++++++++++++++
Physical Form:	BRKXA  imm8
COP (Code of Operation)	 : 0Fh E0h imm8

Clocks:	 12

----------O-BSWAP----------------------------------
OPCODE BSWAP  - Bytes Swap

CPU:  I486 +
Type of Instruction: User

Instruction: BSWAP dwordr

Description:

	     XCHG  BYTE dwordr[31:24],dwordr[7:0]
	     XCHG  BYTE dwordr[23:16],dwordr[15:8]

	     ; Need Good Picture to Show It

Notes: This instruction used for converting big-endian
(Intel) format to little-endian (Motorolla etc.) format.

Flags Affected: None
CPU mode: RM,PM,VM,SMM

Physical Form:		 BSWAP r32
COP (Code of Operation): 0FH 11001rrr  (For 32bit segment)
Clocks: Cyrix Cx486SLC : 4
	      i486     : 1
	      Pentium  : 1
	Cyrix Cx486DX  : 4
	UMC   U5S      : 2
	IBM 486BL3X    : 9

----------O-BTCLR----------------------------------