ports.b

中断列表(4) 712K

 14	NOP (00h) command is supported
 13	Read Buffer command is supported
 12	Write Buffer command is supported
 11	Write Verify command is supported
 10	host protected area feature set is supported
 9	Device Reset (08h) command is supported
 8	Service interrupt is supported
 7	release interrupt is supported
 6	device supports look-ahead
 5	device supports write cache
 4	PACKET command feature set is supported
 3	power management is supported
 2	removable-media feature set is supported
 1	security feature set is supported
 0	SMART feature set is supported
Note:	values of 0000h and FFFFh indicate that this field is not supported
SeeAlso: #P0516,#P0520,#P0521

Bitfields for ATA feature set support/enabled 2:
Bit(s)	Description	(Table P0520)
 15	must be 0 if this field is supported
 14	must be 1 if this field is supported
 13-2	reserved
 1	Read DMA O/Q (C7h) and Write DMA O/Q (CCh) commands supported/enabled
 0	Download Microcode (92h) command is supported/enabled
SeeAlso: #P0516,#P0522,#P0519,#P0521

Bitfields for ATA feature set support extension:
Bit(s)	Description	(Table P0521)
 15	must be 0 if this field is supported
 14	must be 1 if this field is supported
 13-0	reserved
SeeAlso: #P0516,#P0519,#P0520

Bitfields for ATA feature set enabled 1:
Bit(s)	Description	(Table P0522)
 15	Identify Device DMA command is supported
 14	NOP (00h) command is supported
 13	Read Buffer command is supported
 12	Write Buffer command is supported
 11	Write Verify command is supported
 10	host protected area feature set is supported
 9	Device Reset (08h) command is supported
 8	Service interrupt is enabled
 7	release interrupt is enabled
 6	look-ahead is enabled
 5	write cache is enabled
 4	PACKET command feature set is enabled
 3	power management is enabled
 2	removable-media feature set is enabled
 1	security feature set is enabled
 0	SMART feature set is enabled
SeeAlso: #P0516,#P0520

Bitfields for ATA/ATAPI-4 command queueing/overlapped operation support:
Bit(s)	Description	(Table P0523)
 15	reserved
 14	device supports command queueing
 13	device supports overlapped operation
 12-5	reserved
 4-0	maximum depth of queued commands supported (0 if bit 14 clear)
SeeAlso: #P0516

Format of ATAPI Identify Information:
Offset	Size	Description	(Table P0524)
 00h	WORD	general configuration (see #P0525)
 02h  9 WORDs	???
 14h 10 WORDs	serial number
		no serial number if first word is 0000h
		else blank-padded ASCII serial number
 28h  3 WORDs	vendor-specific
 2Eh  4	WORDs	firmware revision
		no revision number if first word is 0000h
		else blank-padded ASCII revision number
 36h 20	WORDs	model number
		no model number if first word is 0000h
		else blank-padded ASCII model string
 5Eh	WORD	vendor-specific
 60h	WORD	reserved (0)
 62h	WORD	capabilities (see #P0518)
 64h	WORD	security mode???
 66h	WORD	PIO data transfer cycle timing
 68h	WORD	single-word DMA data transfer cycle timing
 6Ah	WORD	field validity
		bit 0: offsets 6Ch-73h valid
		bit 1: offsets 80h-8Dh valid
 6Ch	WORD	??? logical cylinders in current translation mode
 6Eh	WORD	??? logical heads in current translation mode
 70h	WORD	??? logical sectors per track in current translation mode
 72h  2	WORDs	??? current capacity in sectors
 76h	WORD	??? multiple-sector count for read/write multiple command
 78h  2	WORDs	??? total number of user-addressable sectors (LBA mode)
 7Ch	WORD	single-word DMA transfer modes
		low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
		high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 7Eh	WORD	multiword DMA transfer
		low byte is bitmap of supported modes (bit 0 = mode 0, etc.)
		high bytes is bitmap of active mode (bit 8 = mode 0, etc.)
 80h	WORD	supported flow control PIO transfer modes
 82h	WORD	minimum multiword DMA transfer cycle time
 84h	WORD	recommended multiword DMA cycle time
 86h	WORD	minimum non-flow-control PIO transfer cycle time
 88h	WORD	minimum PIO transfer cycle time with IORDY
 8Ah  2 WORDs	reserved for future PIO modes (0)
 8Eh	WORD	typical time for release when processing overlapped CMD in
		  microseconds
 90h	WORD	???
 92h	WORD	major ATAPI version number
 94h	WORD	minor ATAPI version number
 96h 54 WORDs	reserved (0)
100h 32 WORDs	vendor-specific
140h 96 WORDs	reserved (0)
SeeAlso: #P0516

Bitfields for ATAPI General Configuration:
Bit(s)	Description	(Table P0525)
 15-14	device type
	0x not ATAPI
	10 ATAPI
	11 reserved
 13	reserved
 12	device present (non-ATAPI)
 12-8	ATAPI device type (see #P0526)
 7	device is removable
 6-5	CMD DMA Request type
	00 microprocessor DRQ
	01 interrupt DRQ
	10 accelerated DRQ
	11 reserved
 4-2	reserved
 1-0	CMD packet size (00 = 12 bytes, 01 = 16 bytes)
SeeAlso: #P0524

(Table P0526)
Values for ATAPI device type:
 00h	direct-access device (i.e. disk drive)
 01h	sequential-access device (i.e. tape drive)
 02h	printer
 03h	processor
 04h	write-once device
 05h	CD-ROM
 06h	scanner
 07h	optical memory
 08h	medium changer
 09h	communications device
 0Ah	reserved for ACS IT8
 0Bh	reserved for ACS IT8
 0Ch	array controller device (i.e. RAID)
 0Dh-1Eh reserved
 1Fh	unknown type or no device
SeeAlso: #P0525

(Table P0527)
Values for Self-Monitoring, Analysis, Reporting Technology (SMART) subcommand:
 D0h	Read Attribute Values (optional) (see #P0529)
	results returned in 512-byte sector read from controller
 D1h	Read Attribute Thresholds (optional) (see #P0528)
	results returned in 512-byte sector read from controller
 D2h	Disable Attribute Autosave (optional)
	sector-count register set to 0000h
 D2h	Enable Attribute Autosave
	sector-count register set to 00F1h
 D3h	Save Attribute Values (optional)
 D4h	execute off-line tests immediately (optional)
 D5h-D6h reserved
 D7h	vendor-specific
 D8h	Enable SMART Operations
 D9h	Disable SMART Operations
 DAh	Return SMART Status
	if any threshold(s) exceeded, CylinderLow set to F4h and CylinderHigh
	  set to 2Ch
 DBh	Enable/Disable Automatic Off-Line Data Collection
	sector-count register set to 0000h to disable, 00F8h to enable
 DCh-DFh reserved
 E0h-EFh vendor-specific
Note:	to access SMART commands, the Cylinder Low register must be set to
	  004Fh and the Cylinder High register must be set to 00C2h before
	  invoking the SMART command with the SMART command number in the
	  Features register
SeeAlso: #P0515

Format of S.M.A.R.T. attribute thresholds sector:
Offset	Size	Description	(Table P0528)
 00h	WORD	data structure revision number (0005h for SMART Revision 2.0)
 02h 12 BYTEs	attribute threshold data 1 (see #P0531)
 ...
14Eh 12 BYTEs	attribute threshold data 30 (see #P0531)
16Ah 18 BYTEs	reserved (0)
17Ch 131 BYTEs	vendor-specific
1FFh	BYTE	checksum (two's complement of eight-bit sum of first 511 bytes)
Note:	if the drive provides fewer than 30 attributes, all remaining attribute
	  records are filled with NUL (00h) bytes
SeeAlso: #P0527,#P0529

Format of S.M.A.R.T. attribute values sector:
Offset	Size	Description	(Table P0529)
 00h	WORD
 02h 12 BYTEs	attribute value data 1 (see #P0532)
 ...
14Eh 12 BYTEs	attribute value data 30 (see #P0532)
16Ah	BYTE	off-line data collection status (see #P0533)
16Bh	BYTE	vendor-specific
16Ch	WORD	time to complete off-line data collection, in seconds
		0001h-FFFFh
16Eh	BYTE	vendor-sepcific
16Fh	BYTE	off-line data collection capability (see #P0534)
170h	WORD	S.M.A.R.T. capabilities (see #P0530)
172h 16 BYTEs	reserved (0)
182h 125 BYTEs	vendor-specific
1FFh	BYTE	checksum (two's complement of eight-bit sum of first 511 bytes)
Note:	if the drive provides fewer than 30 attributes, all remaining attribute
	  records are filled with NUL (00h) bytes
SeeAlso: #P0527,#P0528

Bitfields for S.M.A.R.T capabilities:
Bit(s)	Description	(Table P0530)
 0	attributes saved on going into power-saving mode
 1	Enable/Disable Attribute Autosave subcommands are supported
 2-15	reserved
SeeAlso: #P0529

Format of S.M.A.R.T. attribute threshold:
Offset	Size	Description	(Table P0531)
 00h	BYTE	attribute ID (01h-FFh)
 01h	BYTE	attribute threshold
		00h always passing
		01h minimum threshold value
		FDh maximum threshold value
		FEh invalid (do not use)
		FFh always failing (for testing)
 02h 10 BYTEs	reserved (0)
Note:	the attribute ID and actual threshold values are vendor-specific
SeeAlso: #P0528,#P0532

Format of S.M.A.R.T attribute value:
Offset	Size	Description	(Table P0532)
 00h	BYTE	attribute ID (01h-FFh)
 01h	WORD	status flags
		bit 0: pre-failure/advisory
			=0 value < threshold indicates usage/age exceeding
				  design life
			=1 value < threshold indicates pre-failure condition
		bit 1: on-line data collection
		bits 2-5 vendor-specific
		bits 6-15 reserved
 03h	BYTE	attribute value (01h-FDh)
		initial value prior to data collection is 64h
 04h  8 BYTEs	vendor-specific
SeeAlso: #P0529,#P0531

(Table P0533)
Values for S.M.A.R.T. off-line data collection status:
 00h	off-line collection never started
 01h	reserved
 02h	off-line data collection completed successfully
 03h	reserved
 04h	off-line data collection suspended by command from host
 05h	off-line data collection aborted by command from host
 06h	off-line data collection aborted due to fatal error
 07h-3Fh reserved
 40h-7Fh vendor-specific
 80h	off-line collection never started (auto-offline feature enabled)
 81h	reserved
 82h	off-line data collection completed successfully (auto-offline feature
	  enabled)
 83h	reserved
 84h	off-line data collection suspended by command from host (auto-offline
	  feature enabled)
 85h	off-line data collection aborted by command from host (auto-offline
	  feature enabled)
 86h	off-line data collection aborted due to fatal error (auto-offline
	  feature enabled)
 87h-BFh reserved
 C0h-FFh vendor-specific
SeeAlso: #P0529,#P0534

Bitfields for S.M.A.R.T. off-line data collection capabilities:
Bit(s)	Description	(Table P0534)
 0	Execute Off-Line Immediate (D4h) subcommand is implemented
 1	Enable/Disable Automatic Off-Line subcommand is implemented
 2	abort/resume on interrupting command
	=0 off-line resumes automatically after an interrupting command
	=1 off-line collection is aborted by an interrupting command
 3-7	reserved
SeeAlso: #P0527

(Table P0535)
Values for Feature Code:
 01h	[opt] 8-bit instead of 16-bit data transfers
 02h	[opt] enable write cache
 03h	      set transfer mode as specified by Sector Count register
 04h	[opt] enable all automatic defect reassignment
 22h	[opt] Write Same, user-specified area
 33h	[opt] disable retries
 44h	      specify length of ECC bytes used by Read Long and Write Long
 54h	[opt] set cache segments (value in Sector Count register)
 55h	      disable look-ahead
 66h	      disable reverting to power-on defaults
 77h	[opt] disable ECC
 81h	[opt] 16-bit instead of 8-bit data transfers
 82h	[opt] disable write cache
 84h	[opt] disable all automatic defect reassignment
 88h	[opt] enable ECC
 99h	[opt] enable retries
 9Ah	[opt] set device maximum average current
 AAh	      enable look-ahead
 ABh	[opt] set maximum prefecth (value in Sector Count register)
 BBh	      use four bytes of ECC on Read Long and Write Long (for compat.)
 CCh	      enable reverting to power-on defaults
 DDh	[opt] Write Same, entire disk
SeeAlso: #00266
----------P01F001F6--------------------------
PORT 01F0-01F6 - OPTi "Vendetta" (82C750) CHIPSET - PRIMARY IDE CONTROLLER
Note:	to unlock access to these ports, you must perform two immediately
	  successive 16-bit INs from PORT 01F1h, followed by 8-bit OUT of 03h
	  to PORT 1F2h
SeeAlso: PORT 0170h"Vendetta",PORT 01F0h"HDC 1"

01F0  RW  read cycle timing register (see #P0536)
01F1  RW  write cycle timing register (see #P0537)
01F2  RW  internal ID register (see #P0538)
01F3  RW  control register (see #P0539)
01F5  RW  strap register (see #P0540)
01F6  RW  miscellaneous register (see #P0541)

Bitfields for OPTi "Vendetta" IDE controller read cycle timing register:
Bit(s)	Description	(Table P0536)
 7-4	DRD# pulse width - 1 LCLKs on 16-bit IDE data register read
 3-0	recovery time between DRD# and DA2-0/DCSx# - 2 LCLKs after 16-bit IDE
	  data register read
Notes:	if register 1F6h/176h bit 0 = 0, controls drive selected by
	  register 1F3h/173h bits 3-2
	if register 1F6h/176h bit 0 = 1, controls drive not selected by
	  register 1F3h/173h bits 3-2, if register 1F3h/173h bit 7 = 1
SeeAlso: #P0537,#P0538,#P0539

Bitfields for OPTi "Vendetta" IDE controller write cycle timing register:
Bit(s)	Description	(Table P0537)
 7-4	DWR# pulse width - 1 LCLKs on 16-bit IDE data register write
 3-0	recovery time between DWR# and DA2-0/DCSx# - 2 LCLKs after 16-bit IDE