ports.a

中断列表(4) 712K

 61h	(82C811) command delay (see #P0074)
 62h	(82C811) wait states (see #P0075)
---82C812---
 64h	version (see #P0076)
 65h	ROM configuration
 66h	memory enable 1
 67h	memory enable 2
 68h	memory enable 3
 69h	memory enable 4
 6Ah	bank 0/1 enable
 6Bh	memory configuration
 6Ch	bank 2/3 enable
 6Dh	EMS base address
 6Eh	EMS address extension
 6Fh	miscellaneous
!!!chips\cs8281.pdf p.48

Bitfields for C&T 82C811 processor clock select:
Bit(s)	Description	(Table P0073)
 7-6	82C811 release number (00 = initial release)
 5	fast CPU reset initiated by changing this bit from 0 to 1
 4	processor clock
	0 CLK2IN (default)
	1 BCLK
 3	reserved
 2	enable NMI generate on timeout of local-bus READY# signal
 1	reserved
 0	local-bus READY# signal timed out (128 clock cycles0
SeeAlso: #P0072,#P0074,#P0075

Bitfields for C&T 82C811 command delay register:
Bit(s)	Description	(Table P0074)
 7	enable additional address bus hold time
 6	reserved (1)
 5-4	AT-bus 16-bit memory access delay, in BCLK cycles (default = 0)
 3-2	AT-bus 8-bit memory access delay, in BCLK cycles (default = 1)
 1-0	I/O command delay, in BCLK cycles (default = 1)
SeeAlso: #P0072,#P0073,#P0075

Bitfields for C&T 82C811 wait states register:
Bit(s)	Description	(Table P0075)
 7	80387sx is present
 6	coprocessor is ready
 5-4	AT-bus 16-bit cycle wait states (default = 3)
 3-2	AT-bus 8-bit cycle wait states (00=two ... 11=five [default])
 1-0	bus clock (BCLK)
	00 CLK2IN/2 (default)
	01 CLK2IN/3
	10 ATCLK
	11 reserved
SeeAlso: #P0072,#P0073,#P0074

Bitfields for C&T 82C812 version register:
Bit(s)	Description	(Table P0076)
 7	NEATsx memory controller (0 = 82C812)
 6-5	82C812 revision (00 = initial release)
 4-0	reserved
SeeAlso: #P0072
--------h-P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 84031/84035 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315"

0022  -W  configuration register index (see #P0077)
0023  RW  configuration register data

(Table P0077)
Values for Chips&Technologies 84031/84035 configuration register index:
 01h	(84035) IPC DMA controller wait states and clock (see #P0078)
!!!chips\82310.pdf p.71
!!!chips\api22.pdf p.33
 05h	(84031) ISA-bus command delays (see #P0079)
 06h	(84031) ISA-bus wait states (see #P0080)
 07h	(84031) ISA-bus clock select (see #P0081)
 08h	(84035) performance control (see #P0082)
 09h	(84035) miscellaneous control (see #P0083)
 0Ah	(84035) DMA clock select (see #P0084)
 10h	(84031) DRAM timing (see #P0085)
!!!chips\api22.pdf p.49
 11h	(84031) DRAM setup
 12h	(84031) block 0/1 DRAM configuration
 13h	(84031) block 2/3 DRAM configuration
 14h	(84031) DRAM block 0 start address
 15h	(84031) DRAM block 1 start address
 16h	(84031) DRAM block 2 start address
 17h	(84031) DRAM block 3 start address
 18h	(84031) video shadow / local bus control
 19h	(84031) shadow RAM read enable
 1Ah	(84031) shadow RAM write enable
 1Bh	(84031) ROMCS enable
 1Ch	(84031) soft reset / GATEA20

Bitfields for C&T 84035 IPC DMA controller configuration:
Bit(s)	Description	(Table P0078)
 7-6	reserved
 5-4	wait states for 16-bit DMA
	00 one (default)
	01 two
	10 three
	11 four
 3-2	wait states for 8-bit DMA (settings same as bits 5-4)
 1	disable one-cycle delay of MEMR# signal	after IOR#
 0	DMA clock (0 = BUSCLK/2 [default], 1 = BUSCLK)
SeeAlso: #P0077,#P0082

Bitfields for C&T 84031 ISA-bus command delays:
Bit(s)	Description	(Table P0079)
 !!!
SeeAlso: #P0077,#P0080,#P0081

Bitfields for C&T 84031 ISA-bus wait states:
Bit(s)	Description	(Table P0080)
 !!!
SeeAlso: #P0077,#P0079,#P0081

Bitfields for C&T 84031 ISA-bus clock select:
Bit(s)	Description	(Table P0081)
 !!!
SeeAlso: #P0077,#P0079,#P0080

Bitfields for C&T 84035 performance control:
Bit(s)	Description	(Table P0082)
 7	flush 486 cache during every slow-mode hold (keeps CPU from running out
	  of L1 cache during holds)
 6-0	width of CPU hold pulse in BUSCLKs (0-127)
SeeAlso: #P0077,#P0078,#P0083

Bitfields for C&T 84035 miscellaneous control:
Bit(s)	Description	(Table P0083)
 7	floating-point error mode
	=0 generate IRQ13 internally on FERR#
	=1 use external logic to generate IRQ13
 6	keyboard interrupt mode
	=0 receive IRQ1 directly on IRQ1 pin
	=1 receive IRQ1 over control link
 5	disable GATEA20 emulation
	=0 A20 controlled solely by PORT 0092h
	=1 A20 is OR of PORT 0092h and emulated 8042 A20 control
 4	A20M#/TEST# function
	=0 pin is TEST# input
	=1 pin is A29M# output
 3	reserved
 2	enable 8254 Timer 1 refresh requests
	clearing this bit prevents problems that may be caused by a refresh
	  request which occurs during a reset sequence
 1	use VL-bus-compatible preemptive arbitration for LGNT#
 0	deturbo mode (enable CPU holds as specified by performance-control
	  register) (see #P0082)
Note:	the documentation says that bit 6 should remain clear
SeeAlso: #P0077,#P0082

Bitfields for C&T 84035 DMA clock select:
Bit(s)	Description	(Table P0084)
 7	disable internal real-time clock
 6-4	reserved (0)
 3-0	DMA clock
	0000 SCLK/10
	0001 SCLK/8
	0010 SCLK/6
	1000 SCLK/5 (use with 40 MHz SCLK)
	1001 SCLK/4 (use with 33 MHz SCLK)
	1010 SCLK/3 (use with 25 MHz SCLK)
	1011 SCLK/2.5 (for 20 MHz SCLK)
	1100 SCLK/2 (for 16 MHz SCLK)
	1101 SCLK/1.5
	else reserved
Note:	bits 3-0 should normally be set the same as register 07h bits 3-0
SeeAlso: #P0077

Bitfields for C&T 84031 DRAM timing:
Bit(s)	Description	(Table P0085)
 7-6	reserved (0)
 5
 4
 3
 2	!!!
 1	reserved (0)
 0	read timing
	0 = 3-2-2-2
	1 = 4-3-3-3
SeeAlso: #P0077,#P0086

Bitfields for C&T 84031 DRAM setup:
Bit(s)	Description	(Table P0086)
 7	enable DRAM parity
	(PORT 0061h bits 7 and 2 must also both be clear to enable parity)
 6-4	reserved (0)
 3-0	enable interleave for banks 3-0
	(enabling interleave doubles address range for bank; banks 0/2 and 1/3
	  may be interleaved with each other)
SeeAlso: #P0077,#P0085
----------P00220023--------------------------
PORT 0022-0023 - OPTi 82C206 chipset - CONFIGURATION REGISTERS
Note:	many other OPTi chipsets integrate the functionality of the 82C206, and
	  thus support the 82C206's configuration register (e.g. the
	  82C558 from the Viper chipset)

0022  ?W  index for accesses to data port (set to 01h)
0023  RW  chip set data

Bitfields for OPTi 82C206 configuration register 01h:
Bit(s)	Description	(Table P0087)
 7-6	82C206 wait states
	00 1 SYSCLK
	01 2 SYSCLKs
	10 3 SYSCLKs
	11 4 SYSCLKs (default)
 5-4	number of wait states for 16-bit DMA cycles
	00 1 wait state (default)
	01 2 wait states
	10 3 wait states
	11 4 wait states
 3-2	number of wait states for 8-bit DMA cycles
	00 1 wait state (default)
	01 2 wait states
	10 3 wait states
	11 4 wait states
 1	enable early DMAMEMR#
 0	DMA speed
	0 SYSCLK/2
	1 SYSCLK
----------P00220023--------------------------
PORT 0022-0023 - Intel 82091AA Advanced Integrated Peripheral
Range:	PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
	  PORT 0398h (ISA)
SeeAlso: PORT 0024h"82091AA",PORT 026Eh"82091AA",PORT 0398h"82091AA"

0022  ?W  configuration register index (see #P0088)
0023  RW  configuration register data

(Table P0088)
Values for Intel 82091AA configuration register index:
 00h	product ID (read-only)
	A0h Intel 82091AA
 01h	product revision (read-only) (see #P0089)
 02h	configuration 1 (see #P0090)
 03h	configuration 2 (see #P0091)
 04h-0Fh reserved
 10h	floppy-disk controller configuration (see #P0092)
 11h	floppy-disk controller power management/status (see #P0093)
 12h-1Fh reserved
 20h	parallel port configuration (see #P0094)
 21h	parallel port power management/status (see #P0095)
 22h-2Fh reserved
 30h	serial port A configuration (see #P0096)
 31h	serial port A power management/status (see #P0097)
 32h-3Fh reserved
 40h	serial port B configuration (see #P0096)
 41h	serial port B power management/status (see #P0097)
 42h-4Fh reserved
 50h	IDE configuration (see #P0098)
 51h-FFh reserved

Bitfields for Intel 82091AA product revision register:
Bit(s)	Description	(Table P0089)
 7-4	stepping number 
 3-0	"dash"-number
SeeAlso: #P0088

Bitfields for Intel 82091AA configuration register 1:
Bit(s)	Description	(Table P0090)
 7	unused (0)
 6	supply voltage (read-only) (1 = 3.3V, 0 = 5.0V)
 5-4	configuration mode
	00 software motherboard
	01 software add-in
	10 extended hardware
	11 basic hardware
 3	configuration address (read-only)
	0 primary address (PORT 0022h for X-Bus, PORT 026Eh for ISA)
	1 secondary address (PORT 0024h for X-Bus, PORT 0398h for ISA)
 2-1	reserved
 0	power-down AIP's main clock circuitry
SeeAlso: #P0088,#P0091

Bitfields for Intel 82091AA configuration register 2:
Bit(s)	Description	(Table P0091)
 7-3	IRQ7-IRQ3 mode select
	0 = active high (ISA-compatible tri-state drive)
	1 = active low (EISA-compatible open-collector drive)
 2-0	reserved
SeeAlso: #P0088,#P0090

Bitfields for Intel 82091AA floppy-disk controller configuration register:
Bit(s)	Description	(Table P0092)
 7	four floppy drive support enabled (with external decoder)
 6-2	reserved
 1	FDC address
	0 = primary (03F0h)
	1 = secondary (0370h)
 0	enable FDC
SeeAlso: #P0088,#P0093

Bitfields for Intel 82091AA floppy-disk controller power management register:
Bit(s)	Description	(Table P0093)
 7-4	reserved
 3	enable FDC auto-powerdown on idle
 2	reset FDC
	(this bit must be pulsed, remaining high for at least 1.2 us)
 1	(read-only) FDC is idle
 0	power-down FDC
Note:	to restore FDC from explicit powerdown via bit 0, clear bit 0, then
	  reset the FDC using bit 2 (hardware reset) or using a software reset
	  (FDC's DOR bit 2 or DSR bit 7)
SeeAlso: #P0088,#P0092

Bitfields for Intel 82091AA parallel port configuration:
Bit(s)	Description	(Table P0094)
 7	FIFO threshold
	0 = 8 slots in each direction
	1 = one slot forward, 15 reverse
 6-5	parallel-port hardware mode
	00 ISA-compatible
	01 PS/2-compatible
	10 EPP
	11 ECP (read only -- ECP mode must be set via ECP Extended Control Reg)
 4	reserved
 3	IRQ select
	0 = IRQ5
	1 = IRQ7
 2-1	address select
	00 PORT 0378h-037Bh
	01 PORT 0278h-027Bh
	10 PORT 03BCh-03BEh (not for EPP mode)
	11 reserved
 0	enable parallel port
SeeAlso: #P0088,#P0095,#P0920,PORT 0678h"ECP"

Bitfields for Intel 82091AA parallel port power managment register:
Bit(s)	Description	(Table P0095)
 7-6	reserved
 5	FIFO overrun or underrun has occurred
	this bit is cleared by resetting the port via bit 2
 4	reserved
 3	enable auto-powerdown
 2	reset parallel port (pulse this bit; must remain high for 1.13 us)
 1	(read-only) parallel port is idle
 0	power-down parallel port
Note:	an explicit power-down may be canceled by either clearing bit 0 or
	  pulsing bit 2 to reset the port
SeeAlso: #P0088,#P0094

Bitfields for Intel 82091AA serial port configuration:
Bit(s)	Description	(Table P0096)
 7	enable 2MHz MIDI clock for MIDI baud rate
 6-5	reserved
 4	IRQ select
	0 = IRQ3
	1 = IRQ4
 3-1	address select
	000 PORT 03F8h-03FFh
	001 PORT 02F8h-02FFh
	010 PORT 0220h-0227h
	011 PORT 0228h-022Fh
	100 PORT 0238h-023Fh
	101 PORT 02E8h-02EFh
	110 PORT 0338h-033Fh
	111 PORT 03E8h-03EFh
 0	enable serial port