ports.a

中断列表(4) 712K

Bit(s)	Description	(Table P0050)
  15-8	Reserved
  7	APM SMI Status (RAPMC): set to 1 to indicate that a write to the APM
	  Control Register caused an SMI
  6	EXTSMI# SMI Status (REXT): set to 1 when EXTSMI# caused an SMI
  5	Fast Off Timer Expired Status (RFOT): set to 1 to indicate that the
	  Fast Off Timer expired and caused an SMI.  The Fast Off  timer
	  re-starts counting on the next clock after it expires.
  4	SMI caused by IRQ12
  3	SMI caused by IRQ8
  2	SMI caused by IRQ4
  1	SMI caused by IRQ3
  0	SMI caused by IRQ1
SeeAlso: #P0039
----------P00220023--------------------------
PORT 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP)

0022  RW  chip set data
0023  ?W  index for accesses to data port (see #P0051)

(Table P0051)
Values for Etec Cheetah ET6000 chip set register index:
 10h	system configuration register (see #P0052)
 11h	cache configuration & non-cacheable block size register (see #P0053)
 12h	non-cacheable block address register
	bit 7-1	non-cacheable address, A25-A19
	bit 0	reserved
 13h	DRAM bank & type configuration register (see #P0054)
 14h	DRAM configuration register (see #P0055)
 15h	shadow RAM configuration register (see #P0056)

Bitfields for Etec Cheetah ET6000 system configuration register:
Bit(s)	Description	(Table P0052)
 7-6	00 turbo/non-turbo
	01 local device supported
	10 suspend mode
	11 illegal
 5	reserved
 4	refresh selection
	0 = AT type refresh
	1 = concurrent refresh
 3	slow refresh  95mSec enabled
 2	fast reset delay
	0 = do not use delay
	1 = wait for 2mSec delay
 1	wait for HALT after KBDRST
 0	RAM at A0000-BFFFF
	0 = AT bus cycle
	1 = local bus cycle
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 cache configuration register:
Bit(s)	Description	(Table P0053)
 7-5	000 disabled
	001 512K
	010 1M
	011 2M
	100 4M
	101 8M
	110 16M
	111 32M
 4	DRAM banks
	0 = 2-bank DRAM
	1 = 4-bank DRAM
 3-0	reserved
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 DRAM bank & type configuration register:
Bit(s)	Description	(Table P0054)
 7-6	bank 3 DRAM type
	00 none
	01 256K
	10 1M
	11 4M
 5-4	bank 2 DRAM type
 3-2	bank 1 DRAM type
 1-0	bank 0 DRAM type
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 DRAM configuration register:
Bit(s)	Description	(Table P0055)
 7	on-board memory range 15M to 16M disabled
 6	on-board memory range 512K-640K disabled
 5	ROM chip select at C0000-DFFFF enabled
 4	RAS to CAS time
	0 = 1 SYSCLCK,	not for R0WS
	1 = 2 SYSCLCK
 3	RAS precharge time
	0 = 1.5 SYSCLCK
	1 = 2.5 SYSCLCK
 2-1	read cycle wait state
	00 = 0 wait state
	01 = 1 ws
	10 = 2 ws
	11 = 3 ws
 0	write cycle wait state
	0 = 0 ws
	1 = 1 ws
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 shadow RAM configuration register:
Bit(s)	Description	(Table P0056)
 7	shadow at C0000-FFFFF
	0 = non-cacheable
	1 = cacheable and cache-write-proteced
 6	access ROM/RAM at F0000-FFFFF
	0 = read from ROM, write to RAM
	1 = read from shadow, write is protected
 5	access ROM/RAM at E0000-EFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow E0000-EFFFF enabled
 4	RAM at E0000-EFFFF is read-only
 3	access ROM/RAM at D0000-DFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow D0000-DFFFF enabled
 2	RAM at D0000-DFFFF is read-only
 1	access ROM/RAM at C0000-CFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow C0000-CFFFF enabled
 0	RAM at C0000-CFFFF is read-only
SeeAlso: #P0051
----------P00220023--------------------------
PORT 0022-0023 - Hewlett-Packard Hornet chipset (HP 100LX/200LX)

0022  RW  index for accesses to data port (see Table P189)
0023  RW  chip set data

(Table P0057)
Values for HP Hornet chipset register index:
 1Eh	buzzer volume/clock oscillator speed
	bit 7-6: buzzer volume
	bit 5-4: system oscillator speed
		00: 10.738636MHz
		01: 15.836773MHz(HP 100/200LX has oscillator with this speed)
		10: 21.477272MHz
		11: 31.673550MHz
 21h	display timing???
 23h	LCD contrast (see INT15h AH=62h)
	valid values: 00h-1fh (1fh is the darkest)
 51h	power adapter status
	bit 7-1: ???
	bit 0: power adapter status(0=inactive/1=active)
 52h	nicad charge status
	bit 7-3: ???
	bit 2: battery charging status(0=???/1=slow charge)
	bit 1-0: ???
 53h	nicad charge status
	bit 7-1: ???
	bit 0: battery charging status(0=???/1=fast charge)
 80h	memory wait for internal ROM
	valid values: 00h-07h
 81h	memory wait for internal RAM
	valid values: 00h-03h
 82h	memory wait for external RAM
	valid values: 00h-0fh
 87h	battery status???
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C100/110 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0058)
0023  RW  configuration register data

(Table P0058)
Values for Chips&Technologies 82C100/110 configuration register index:
 40h	clock mode/size (see #P0059)
 41h	system configuration (see #P0060)
 42h	configuration valid (see #P0061)
 43h	DIP switch emulation (see #P0062)
 44h-47h substitute NMI vector, bytes 0-3
	(these specify the vector to be substituted at the INT 02 vector's
	  memory address whenever an NMI occurs, preventing application
	  software from modifying the NMI handler)
 48h	refresh timer counter (see #P0063)
 49h	wait state select, refresh enable, keyboard type (see #P0064)
 4Ah	reserved
 4Bh	sleep/memory configuration (see #P0065)
 4Ch	EMS configuration (see #P0066)
 4Dh-4Fh reserved

Bitfields for Chips&Technologies 82C100 clock mode/size register:
Bit(s)	Description	(Table P0059)
 !!!
!!!chips\82c110.pdf p.35
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 system configuration register:
Bit(s)	Description	(Table P0060)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 configuration valid register:
Bit(s)	Description	(Table P0061)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C110 DIP Switch Emulation register:
Bit(s)	Description	(Table P0062)
 !!!chips\82c110.pdf p.36
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 refresh timer count register:
Bit(s)	Description	(Table P0063)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 wait state select register:
Bit(s)	Description	(Table P0064)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 sleep/memory configuration:
Bit(s)	Description	(Table P0065)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 EMS configuration register:
Bit(s)	Description	(Table P0066)
 !!!
SeeAlso: #P0058
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C235 "SCAT" - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0067)
0023  RW  configuration register data

(Table P0067)
Values for Chips&Technologies 82C235 configuration register index:
 01h	DMA wait-state control
 40h	version (read-only)
 41h	clock control
 42h-43h reserved (but listed as read-write in docs)
 44h	peripheral control
 45h	miscellaneous status
 46h	power management
 47h	reserved
 48h	ROM enable
 49h	RAM write-protect control
 4Ah	shadow RAM enable 1
 4Bh	shadow RAM enable 2
 4Ch	shadow RAM enable 3
 4Dh	DRAM configuration
 4Eh	extended boundary
 4Fh	EMS control
 !!!chips\82c235.pdf p.87, p.140
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C311 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0068)
0023  RW  configuration register data

(Table P0068)
Values for Chips&Technologies 82C311 configuration register index:
 04h	version (read-only)   !!!chips\82c311.pdf p.65
 05h	AT-bus command delay
 06h	AT-bus wait-state control
 08h	identification
 09h	low RAM/ROM configuration
 0Ch	memory enable map (80000h-9FFFFh)
 0Dh	memory enable map (A0000h-BFFFFh)
 0Eh	memory enable map (C0000h-DFFFFh)
 0Fh	memory enable map (E0000h-FFFFFh)
 10h	block 0 type and start address
 11h	block 0 DRAM timing
 12h	block 1 type and start address
 13h	block 1 DRAM timing
 14h	block 2 type and start address
 15h	block 2 DRAM timing
 16h	block 3 type and start address
 17h	block 3 DRAM timing
 18h	memory block types
 20h	cache control
 21h	directory RAM control 1
 22h	tag RAM directory address (low)
 23h	reference location
 24h	SRAM configuration/direct access address
 25h	directory RAM control 2
 26h	READY timeout
 28h	error source/address
 29h	error address (bits 23-16)
 2Ah	memory enable map (00000h-7FFFFh)
 2Bh	miscellaneous control
 2Ch	middle RAM/ROM configuration
 2Fh	page mode posted-write control (82C311 rev. C only)
 30h	block 0 non-cacheable address (bits 23-16)
 31h	block 0 non-cacheable address (bits 15-12) and size
 32h	block 1 non-cacheable address (bits 23-16)
 33h	block 1 non-cacheable address (bits 15-12) and size
 34h	block 2 non-cacheable address (bits 23-16)
 35h	block 2 non-cacheable address (bits 15-12) and size
 36h	block 3 non-cacheable address (bits 23-16)
 37h	block 3 non-cacheable address (bits 15-12) and size
 38h	block 0/1 non-cacheable addresses (bits 26-24)
 39h	block 2/3 non-cacheable addresses (bits 26-24)
 60h	fast reset control
!!!chips\82c311.pdf p.76, p.115
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C315 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C316"

0022  -W  configuration register index (see #P0069)
0023  RW  configuration register data

(Table P0069)
Values for Chips&Technologies 82C315 configuration register index:
 07h	processor and bus clock source selection (see #P0070)

Bitfields for C&T 82C315 clock source selection register:
Bit(s)	Description	(Table P0070)
 7-5	reserved (0)
 4	80387 is present
 3	processor clock select
	=0 CLK2IN
	=1 AT bus state machine clock
 2-0	bus clock source select
	000 CLK2IN/5
	001 CLK2IN/4
	010 CLK2IN/3
	011 CLK2IN/2
	100 ATCLK
SeeAlso: #P0069
----------P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C316 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315",PORT 0022h"82C811"

0022  -W  configuration register index (see #P0071)
0023  RW  configuration register data

(Table P0071)
Values for Chips&Technologies 82C316 configuration register index:
 01h	clock/wait-state control	!!!chips\cs8233.pdf p.178
 26h	RTC/NMI/Coprocessor reset	!!!chips\cs8233.pdf p.231
 71h	programmable I/O port 1 address, bits 15-8
 72h	programmable I/O port 1 address, bits 7-0
 73h	programmable I/O port 1 enable
 74h	programmable I/O port 2 address, bits 15-8
 75h	programmable I/O port 2 address, bits 7-0
 76h	programmable I/O port 2 enable
 77h	programmable I/O port 3 address, bits 15-8
 78h	programmable I/O port 3 address, bits 7-0
 79h	programmable I/O port 3 enable
SeeAlso: #P0069
--------h-P00220023--------------------------
PORT 0022-0023 - Chips&Technologies 82C811/82C812 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315"

0022  -W  configuration register index (see #P0072)
0023  RW  configuration register data

(Table P0072)
Values for Chips&Technologies 82C811/812 configuration register index:
 60h	(82C811) processor clock select (see #P0073)