ports.a

中断列表(4) 712K

 CFh	non-cacheable region 4, start addr 15-12, size (low nibble) (see #P0018)
SeeAlso: #P0023,#P0021

(Table P0018)
Values for Cyrix Cx486SLC/DLC non-cacheable region sizes:
 00h	disabled
 01h	4K
 02h	8K
 03h	16K
 04h	32K
 05h	64K
 06h	128K
 07h	256K
 08h	512K
 09h	1M
 0Ah	2M
 0Bh	4M
 0Ch	8M
 0Dh	16M
 0Eh	32M
 0Fh	4G
SeeAlso: #P0017

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0:
Bit(s)	Description	(Table P0019)
 0	"NC0" first 64K of each 1M noncacheable in real/V86
 1	"NC1" 640K-1M noncacheable
 2	"A20M" enables A20M# input pin
 3	"KEN"  enables KEN# input pin
 4	"FLUSH" enables FLUSH input pin
 5	"BARB" enables internal cache flushing on bus holds
 6	"C0" cache direct-mapped instead of 2-way associative
 7	"SUSPEND" enables SUSP# input and SUSPA# output pins
SeeAlso: #P0017,#P0020,#P0032

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1:
Bit(s)	Description	(Table P0020)
 0	"RPL" enables output pins RPLSET and RPLVAL#
SeeAlso: #P0017,#P0019,#P0024
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 486S2/D2/DX/DX2/DX4 PROCESSOR - CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0021)
0023  RW  cache configuration register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0021)
Values for Cyrix 486S2/D2/DX/DX2/DX4 configuration register number:
 C2h	CR2 (see #P0025)
 C3h	CR3 (see #P0026)
 CDh	SMM region, start address bits 31-24
 CEh	SMM region, start address bits 23-16
 CFh	SMM region, start addr 15-12, size (low nibble) (see #P0018)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0023,#P0031

(Table P0022)
Values for Cyrix device identification:
(#0 /#1)
 00h	Cx486SLC
 01h	Cx486DlC
 02h	Cx486SLC2
 03h	Cx486DLC2
 04h	Cx486SRx
 05h	Cx486DRx
 06h	Cx486SRx2
 07h	Cx486DRx2
 10h	Cx486S (B-step)
 11h	Cx486S2 (B-step)
 12h	Cx486Se (B-step)
 13h	Cx486S2e (B-step)
1Ah/05h	Cx486DX-40
1Bh/08h	Cx486DX2-50
1Bh/0Bh	Cx486DX2-66
1Bh/31h	Cx486DX2-v80
1Fh/36h	Cx486DX4-v100
 28h	5x86 1xs
 29h	5x86 2xs
 2Ah	5x86 1xp
 2Bh	5x86 2xp
 2Ch	5x86 4xs
 2Dh	5x86 3xs
 2Eh	5x86 4xp
 2Fh	5x86 3xp
 30h	6x86 1xs
 31h	6x86 2xs
 32h	6x86 1xp
 33h	6x86 2xp
 34h	6x86 4xs
 35h	6x86 3xs
 36h	6x86 4xp
 37h	6x86 3xp
Note:	#0 is the value in configuration register FEh, while #1 is the value
	  in configuration register FFh
SeeAlso: #P0021
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0023)
0023  RW  configuration control register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0023)
Values for Cyrix 5x86 configuration registers:
 20h	Performance Control (see #P0028)
 C1h	Configuration Control #1 (CCR1) (see #P0024)
 C2h	Configuration Control #2 (CCR2) (see #P0025)
 C3h	Configuration Control #3 (CCR3) (see #P0026)
 CDh	System Memory Management address region #0 (smar0) (see #P0029)
 CEh	System Memory Management address region #1 (smar1)
 CFh	System Memory Management address region #2 (smar2)
 E8h	Configuration Control Register 4
 F0h	Power Management (see #P0030)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0021,#P0031

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 1 (CCR1):
Bit(s)	Description	(Table P0024)
 0	reserved
 1	enable SMM pins
 2	system management memory access
 3	main memory access
 4	(6x86) no LOCK during bus cycles
 6-5	reserved
 7	(6x86) use address region 3 as SMM space
Note:	bits 1,2,7 may only be written when CCR3 bit 0 is enabled
SeeAlso: #P0020,#P0025,#P0026,#P0027

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 2 (CCR2):
Bit(s)	Description	(Table P0025)
 0	reserved
 1	enable write-back cache interface pins
 2	lock NW bit
 3	suspend on HLT instruction
 4	write-through region 1
 5	reserved
 6	enable burst write cycles
 7	enable suspend pins
SeeAlso: #P0024,#P0026,#P0027

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 3 (CCR3):
Bit(s)	Description	(Table P0026)
 0	SMM register lock (can only be cleared in SMM mode or by CPU reset)
 1	NMI enable
 2	linear address burst cycles (5x86,6x86 only)
	=0 Pentium-compatible
	=1 linear sequencing
 3	SMM mode (5x86 only)
	=0 486SL
	=1 Cyrix
 7-4	map enable (5x86,6x86 only)
	0000 only allow access to configuration registers C0h-CFh,FEh,FFh
	0001 enable access to all configuration registers
SeeAlso: #P0024,#P0025,#P0027,#P0028,#P0030

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 4 (CCR4):
Bit(s)	Description	(Table P0027)
 2-0	I/O recovery time (000 = none, else 2^N clocks)
 3	enable memory-read bypassing (5x86 only)
 4	enable directory table entry cache
 6-5	reserved
 7	enable CPUID instruction (stepping 1+ and Cx6x86)
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P0024,#P0025,#P0026

Bitfields for Cyrix 5x86 Performance Control register:
Bit(s)	Description	(Table P0028)
 0	return stack enabled (speculatively execute code after current CALL)
 1	branch-target buffer enabled
 2	loop enable
 6-3	reserved (0)
 7	load-store serialization enabled
	(memory reads and writes may be reorganized into optimum order)
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P0030,#P0024

Bitfields for Cyrix 5x86 SMM Address Region register:
Bit(s)	Description	(Table P0029)
 3-0	block size
 23-4	starting address

Bitfields for Cyrix 5x86 Power Management register:
Bit(s)	Description	(Table P0030)
 1-0	core clock to bus clock ratio
	00 1:1
	01 2:1
	10 reserved
	11 3:1
 2	CPU running at half bus speed, ignore bits 1-0
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
----------P00220023--------------------------
PORT 0022-0023 - Cyrix 6x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486",PORT 0022h"5x86"

0022  -W  index for accesses to next port (see #P0023)
0023  RW  configuration control register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0031)
Values for Cyrix 6x86 configuration registers:
 C0h	Configuration Control Register 0 (CCR0) (see #P0032)
 C1h	Configuration Control #1 (CCR1) (see #P0024)
 C2h	Configuration Control #2 (CCR2) (see #P0025)
 C3h	Configuration Control #3 (CCR3) (see #P0026)
 C4h	Address region 0 (bits 31-24)
 C5h	Address region 0 (bits 23-16)
 C6h	Address region 0 (bits 15-12 and size)
 C7h	Address region 1 (bits 31-24)
 C8h	Address region 1 (bits 23-16)
 C9h	Address region 1 (bits 15-12 and size)
 CAh	Address region 2 (bits 31-24)
 CBh	Address region 2 (bits 23-16)
 CCh	Address region 2 (bits 15-12 and size)
 CDh	Address region 3 (bits 31-24)
 CEh	Address region 3 (bits 23-16)
 CFh	Address region 3 (bits 15-12 and size)
 D0h	Address region 4 (bits 31-24)
 D1h	Address region 4 (bits 23-16)
 D2h	Address region 4 (bits 15-12 and size)
 D3h	Address region 5 (bits 31-24)
 D4h	Address region 5 (bits 23-16)
 D5h	Address region 5 (bits 15-12 and size)
 D6h	Address region 6 (bits 31-24)
 D7h	Address region 6 (bits 23-16)
 D8h	Address region 6 (bits 15-12 and size)
 D9h	Address region 7 (bits 31-24)
 DAh	Address region 7 (bits 23-16)
 DBh	Address region 7 (bits 15-12 and size)
 DCh	Region Control 0
 DDh	Region Control 1
 DEh	Region Control 2
 DFh	Region Control 3
 E0h	Region Control 4
 E1h	Region Control 5
 E2h	Region Control 6
 E3h	Region Control 7
 E8h	Configuration Control Register 4 (see #P0027)
 E9h	Configuration Control Register 5 (see #P0033)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0023

Bitfields for Cyrix 6x86 Configuration Control Register 0:
Bit(s)	Description	(Table P0032)
 7-2	???
 1	address region 640K-1M is noncacheable
 0	???
SeeAlso: #P0019

Bitfields for Cyrix 6x86 Configuration Control Register 5:
Bit(s)	Description	(Table P0033)
 7-6	reserved
 5	enable all address-region registers (control registers C4h-DBh)
 4	assert LBA# pin on all accesses to 640K-1M
 3-1	reserved
 0	allocate new cache lines only on read misses
SeeAlso: #P0032,#P0027,#P0031
----------P00220023--------------------------
PORT 0022-0023 - GoldStar 286 - CHIP SET CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0034)
0023  RW  configuration control register array (indexed by PORT 0022h)

(Table P0034)
Values for GoldStar 286 chipset configuration register index:
 60h	turbo control
	write 00h to PORT 0023h to turn on turbo, 10h to turn it off
--------X-P00220023--------------------------
PORT 0022-0023 - Intel 82358DT 'Mongoose' EISA CHIPSET - 82359 DRAM CONTROLLER
Notes:	this chip uses a chip ID of 01
	the LIM register herein use a chip ID of 1A
Index: Intel 82351

0022  -W  index for accesses to data port (see #P0036,#P0037,#P0038)
0023  RW  chip set data

(Table P0035)
Values for Intel 82351/82359 chip ID:
 01h	82359 DRAM controller, general registers
 02h	82351 EISA local I/O support
 A1h	82359 DRAM controller, EMS registers
 FFh	no chip accessible (default)
SeeAlso: #P0036,#P0037,#P0038

(Table P0036)
Values for 82359 DRAM controller general register index:
 00h	DRAM bank 0 type
	bit 7	unknown
	bit 6-4	000 DRAM in bank 0 (standard)
		001 bank 1
		010 bank 2
		011 bank 3
		100 banks 0,1
		101 banks 2,3
		110 banks 0,1,2,3
		111 empty (standard for 1,2,3)
	bit 3-2	unknown
	bit 1-0	00 64K chips used
		01 256K
		10 1M
		11 4M
 01h	DRAM bank 1 type
 02h	DRAM bank 2 type
 03h	DRAM bank 3 type
 04h	DRAM speed detection/selection
 05h	DRAM interleave control
 06h	RAS line mode
 07h	cache-enable selection
 08h	mode register A (DRAM, cache)
 09h	mode register B (cache, burst modes, BIOS size)
 0Ah	mode register C (concurrency control, burst/cycle speed)
 10h	host timing
 11h	host-system delay timing
 12h	system timing
 13h	DRAM row precharge time
 14h	DRAM row timing
 15h	DRAM column timing
 16h	CAS pulse width
 17h	CAS-to-MDS delay
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 28h-2Ch	parity-error trap address
 30h	page hit cycle length (read)
 31h	page miss cycle length (read)
 32h	row miss cycle length (read)
 33h	page hit cycle length (write)
 34h	page miss cycle length (write)
 35h	row miss cycle length (write)
 40h	memory enable 00000h-7FFFFh
 41h	memory enable 80000h-9FFFFh
 42h	memory enable A0000h-AFFFFh
 43h	memory enable B0000h-BFFFFh
 44h	memory enable C0000h-CFFFFh
 45h	memory enable D0000h-DFFFFh
 46h	memory enable E0000h-EFFFFh
 47h	memory enable F0000h-FFFFFh
 4Eh	remap 80000h-FFFFFh to extended memory
 50h-53h	programmable attribute map 1
 54h-57h	programmable attribute map 2
 58h-5Bh	programmable attribute map 3
 5Ch-5Fh	programmable attribute map 4
 83h-84h	split address register (address bits A31-A20)
 85h	cache control