ports.a

中断列表(4) 712K

PORTS LIST			Release 60		Last change 03jan99
Copyright (c) 1989,1990,1991,1992,1993,1994,1995,1996,1997,1998,1999 Ralf Brown
[This file originally by Wim Osterholt <[e-mail]>,
 though it has grown considerably since.]

		XT, AT and PS/2	 I/O port addresses

Do NOT consider this information to be complete and accurate.  If you want
to do hardware programming ALWAYS check the appropriate data sheets (but
even they are sometimes in error!).  Be aware that erroneous port programming
can put your data or even your hardware at risk.

There are a number of memory-mapped addresses in use for I/O; see MEMORY.LST
for details on memory-mapped I/O.

--------!---Note-----------------------------
Note: the port description format is:

PPPPw RW  description

where:	PPPP	is the four-digit hex port number or a plus sign and three hex
		digits to indicate an offset from a base port address
	w	is blank for byte-size port, 'w' for word, and 'd' for dword
	R	is dash (or blank) if not readable, 'r' if sometimes readable,
		'R' if "always" readable, '?' if readability unknown
	W	is dash (or blank) if not writable, 'w' if sometimes writable,
		'W' if "always" writable, 'C' if write-clear, and
		'?' if writability unknown
----------P0000001F--------------------------
PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
SeeAlso: PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0000  R-  DMA channel 0	current address		byte  0, then byte 1
0000  -W  DMA channel 0	base address		byte  0, then byte 1
0001  RW  DMA channel 0 word count		byte 0, then byte 1
0002  R-  DMA channel 1	current address		byte  0, then byte 1
0002  -W  DMA channel 1	base address		byte  0, then byte 1
0003  RW  DMA channel 1 word count		byte 0, then byte 1
0004  R-  DMA channel 2	current address		byte  0, then byte 1
0004  -W  DMA channel 2	base address		byte  0, then byte 1
0005  RW  DMA channel 2 word count		byte 0, then byte 1
0006  R-  DMA channel 3	current address		byte  0, then byte 1
0006  -W  DMA channel 3	base address		byte  0, then byte 1
0007  RW  DMA channel 3 word count		byte 0, then byte 1

0008  R-  DMA channel 0-3 status register (see #P0001)
0008  -W  DMA channel 0-3 command register (see #P0002)
0009  -W  DMA channel 0-3 write request register (see #P0003)
000A  RW  DMA channel 0-3 mask register (see #P0004)
000B  -W  DMA channel 0-3 mode register (see #P0005)

000C  -W  DMA channel 0-3 clear byte pointer flip-flop register
	  any write clears LSB/MSB flip-flop of address and counter registers
000D  R-  DMA channel 0-3 temporary register
000D  -W  DMA channel 0-3 master clear register
	  any write causes reset of 8237
000E  -W  DMA channel 0-3 clear mask register
	  any write clears masks for all channels
000F  rW  DMA channel 0-3 write mask register (see #P0006)
Notes:	the temporary register is used as holding register in memory-to-memory
	  DMA transfers; it holds the last transferred byte
	channel 2 is used by the floppy disk controller
	on the IBM PC/XT channel 0 was used for the memory refresh and
	  channel 3 was used by the hard disk controller
	on AT and later machines with two DMA controllers, channel 4 is used
	  as a cascade for channels 0-3
	command and request registers do not exist on a PS/2 DMA controller

Bitfields for DMA channel 0-3 status register:
Bit(s)	Description	(Table P0001)
 7	channel 3 request active
 6	channel 2 request active
 5	channel 1 request active
 4	channel 0 request active
 3	channel terminal count on channel 3
 2	channel terminal count on channel 2
 1	channel terminal count on channel 1
 0	channel terminal count on channel 0
SeeAlso: #P0002,#P0481

Bitfields for DMA channel 0-3 command register:
Bit(s)	Description	(Table P0002)
 7	DACK sense active high
 6	DREQ sense active high
 5	=1 extended write selection
	=0 late write selection
 4	rotating priority instead of fixed priority
 3	compressed timing (two clocks instead of four per transfer)
	=1 normal timing (default)
	=0 compressed timing
 2	=1 enable controller
	=0 enable memory-to-memory
 1-0	channel number
SeeAlso: #P0001,#P0004,#P0005,#P0482

Bitfields for DMA channel 0-3 request register:
Bit(s)	Description	(Table P0003)
 7-3	reserved (0)
 2	=0 clear request bit
	=1 set request bit
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0004

Bitfields for DMA channel 0-3 mask register:
Bit(s)	Description	(Table P0004)
 7-3	reserved (0)
 2	=0 clear mask bit
	=1 set mask bit
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0001,#P0002,#P0003,#P0484

Bitfields for DMA channel 0-3 mode register:
Bit(s)	Description	(Table P0005)
 7-6	transfer mode
	00 demand mode
	01 single mode
	10 block mode
	11 cascade mode
 5	direction
	=0 increment address after each transfer
	=1 decrement address
 3-2	operation
	00 verify operation
	01 write to memory
	10 read from memory
	11 reserved
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0002,#P0485

Bitfields for DMA channel 0-3 write mask register:
Bit(s)	Description	(Table P0006)
 7-4	reserved
 3	channel 3 mask bit
 2	channel 2 mask bit
 1	channel 1 mask bit
 0	channel 0 mask bit
Note:	each mask bit is automatically set when the corresponding channel
	  reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P0004,#P0486
----------P0010001F--------------------------
PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80
SeeAlso: PORT 0000h-001Fh,PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0018  -W  extended function register (see #P0007)
001A  -W  extended function execute register

Bitfields for DMA extended function register:
Bit(s)	Description	(Table P0007)
 7-4	function code (see #P0008)
 3	reserved (0)
 2-0	channel number
	000 channel 0 select
	001 channel 1 select
	010 channel 2 select
	011 channel 3 select
	100 channel 4 select
	101 channel 5 select
	110 channel 6 select
	111 channel 7 select

(Table P0008)
Values for DMA extended function codes (data go to/from PORT 001Ah):
Value	Description		  Parameters  Results
 00h	current address register      -	      CA0,CA1
 02h	write address		      -	      A0,A1,P
 03h	read  address		   A0,A1,P	 -
 04h	write word count register   C0,C1	 -
 05h	read  word count register     -	       C0,C1
 06h	read status register	      -		 S
 07h	mode register		      -		 M
 09h	mask channel		      -		 -
 0Ah	unmask channel		      -		 -
 0Dh	master clear		      -		 -
Note:	CA0/CA1	  LSB/MSB of the current address register
	A0/A1	  LSB/MSB of the base address register
	P	  DMA page address
	C0/C1	  LSB/MSB of the word count register
	S	  status register value (see #P0001, #P0481)
	M	  mode register value (see #P0005, #P0485)
	first, the extended function register is written, then the extended
	  function register execute register is read/written if the function
	  being executing requires

Bitfields for DMA extended mode register:
Bit(s)	Description	(Table P0009)
 7	reserved (0)
 6	=0 8-bit transfer
	=1 16-bit transfer
 5-4	reserved (0)
 3	transfer type
	=0 read from memory
	=1 write to memory
 2	=0 disable memory write
	=1 enable  memory write
 1	reserved (0)
 0	address select
	=0 use 0 as base address
	=1 use a value from base address register
Note:	the IBM PS/2 model 80 technical reference doesn't seem to mention this
	  register's address
----------P0020003F--------------------------
PORT 0020-003F - PIC 1 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 00A0h-00AFh"PIC 2",INT 08"IRQ0",INT 0F"IRQ7"

0020  -W  PIC initialization command word ICW1 (see #P0010)
0020  -W  PIC output control word OCW2 (see #P0015)
0020  -W  PIC output control word OCW3 (see #P0016)
0020  R-  PIC  interrupt request/in-service registers after OCW3
		request register:
		 bit 7-0 = 0  no active request for the corresponding int. line
			 = 1  active request for corresponding interrupt line
		in-service register:
		 bit 7-0 = 0  corresponding line not currently being serviced
			 = 1  corresponding int. line currently being serviced

0021  -W  PIC ICW2,ICW3,ICW4 immed after ICW1 to 0020 (see #P0011,#P0012,#P0013)
0021  RW  PIC master interrupt mask register OCW1 (see #P0014)

Bitfields for PIC initialization command word ICW1:
Bit(s)	Description	(Table P0010)
 7-5	0 (only used in 8080/8085 mode)
 4	ICW1 is being issued
 3	(LTIM)
	=0  edge triggered mode
	=1  level triggered mode
 2	interrupt vector size
	=0 successive interrupt vectors use 8 bytes (8080/8085)
	=1 successive interrupt vectors use 4 bytes (80x86)
 1	(SNGL)
	=0  cascade mode
	=1  single mode, no ICW3 needed
 0	ICW4 needed
SeeAlso: #P0011,#P0012,#P0013

Bitfields for PIC initialization command word ICW2:
Bit(s)	Description	(Table P0011)
 7-3	address lines A0-A3 of base vector address for PIC
 2-0	reserved
SeeAlso: #P0010,#P0012,#P0013

Bitfields for PIC initialization command word ICW3:
Bit(s)	Description	(Table P0012)
 7-0	=0 slave controller not attached to corresponding interrupt pin
	=1 slave controller attached to corresponding interrupt pin
SeeAlso: #P0010,#P0011,#P0013

Bitfields for PIC initialization command word ICW4:
Bit(s)	Description	(Table P0013)
 7-5	reserved (0)
 4	running in special fully-nested mode
 3-2	mode
	0x nonbuffered mode
	10 buffered mode/slave
	11 buffered mode/master
 1	Auto EOI
 0	=0  8085 mode
	=1  8086/8088 mode
SeeAlso: #P0010,#P0011,#P0012

Bitfields for PIC output control word OCW1:
Bit(s)	Description	(Table P0014)
 7	disable IRQ7 (parallel printer interrupt)
 6	disable IRQ6 (diskette interrupt)
 5	disable IRQ5 (fixed disk interrupt)
 4	disable IRQ4 (serial port 1 interrupt)
 3	disable IRQ3 (serial port 2 interrupt)
 2	disable IRQ2 (video interrupt)
 1	disable IRQ1 (keyboard, mouse, RTC interrupt)
 0	disable IRQ0 (timer interrupt)
SeeAlso: #P0015,#P0016,#P0418

Bitfields for PIC output control word OCW2:
Bit(s)	Description	(Table P0015)
 7-5	operation
	000 rotate in auto EOI mode (clear)
	001 (WORD_A) nonspecific EOI
	010 (WORD_H) no operation
	011 (WORD_B) specific EOI
	100 (WORD_F) rotate in auto EOI mode (set)
	101 (WORD_C) rotate on nonspecific EOI command
	110 (WORD_E) set priority command
	111 (WORD_D) rotate on specific EOI command
 4-3	reserved (00 - signals OCW2)
 2-0	interrupt request to which the command applies
	(only used by WORD_B, WORD_D, and WORD_E)
SeeAlso: #P0014,#P0016

Bitfields for PIC output control word OCW3:
Bit(s)	Description	(Table P0016)
 7	reserved (0)
 6-5	special mask
	0x  no operation
	10  reset special mask
	11  set special mask mode
 4-3	reserved (01 - signals OCW3)
 2	poll command
 1-0	function
	0x  no operation
	10  read interrupt request register on next read from PORT 0020h
	11  read interrupt in-service register on next read from PORT 0020h
Note:	the special mask mode permits all other interrupts (even those with
	  lower priority) to be processed while an interrupt is already in
	  service, but will not re-issue an interrupt for a particular IRQ
	  while it remains in service
SeeAlso: #P0014,#P0015
----------P0022------------------------------
PORT 0022 - Intel 82439TX Chipset - Power Control register
SeeAlso: PORT 0022h"82443BX"

0022  RW  PM2 Register Block
	bits 7-1: reserved
	bit 0:	Arbiter Disable
--------p-P0022------------------------------
PORT 0022 - Intel 82443BX - "PM2_CTL" ACPI Power Control 2 Register
SeeAlso: PORT 0022h"82439TX",#01142 at INT 1A/AX=B10Ah/SF=8086h

0022  RW  ACPI Power Control Register 2
	bits 7-1: reserved
	bit 0:	disable primary PCI and AGP arbiter requests
----------P00220023--------------------------
PORT 0022-0023 - CHIP SET DATA
Note:	These two ports are used by numerous chipsets.	Various chipsets are
	  detailed below.

0022  -W  index for accesses to data port
0023  RW  chip set data
----------P00220023--------------------------
PORT 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0017)
0023  RW  cache configuration register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0017)
Values for Cyrix Cx486SLC/DLC Cache Configuration register number:
 C0h	CR0 (see #P0019)
 C1h	CR1 (see #P0020)
 C4h	non-cacheable region 1, start address bits 31-24
 C5h	non-cacheable region 1, start address bits 23-16
 C6h	non-cacheable region 1, start addr 15-12, size (low nibble) (see #P0018)
 C7h	non-cacheable region 2, start address bits 31-24
 C8h	non-cacheable region 2, start address bits 23-16
 C9h	non-cacheable region 2, start addr 15-12, size (low nibble) (see #P0018)
 CAh	non-cacheable region 3, start address bits 31-24
 CBh	non-cacheable region 3, start address bits 23-16
 CCh	non-cacheable region 3, start addr 15-12, size (low nibble) (see #P0018)
 CDh	non-cacheable region 4, start address bits 31-24
 CEh	non-cacheable region 4, start address bits 23-16