msr.lst

中断列表(2) 352K

----------S00000403--------------------------
MSR 00000403h - Pentium Pro - "MC0_MISC"
SeeAlso: MSR 00000401h,MSR 00000402h
----------S00000404--------------------------
MSR 00000404h - Pentium Pro - "MC1_CTL" Machine Check Control 1
SeeAlso: MSR 00000400h,MSR 00000408h
----------S00000405--------------------------
MSR 00000405h - Pentium Pro - "MC1_STATUS" Machine Check Status 1
----------S00000406--------------------------
MSR 00000406h - Pentium Pro - "MC1_ADDR" Machine Check Address 1
----------S00000407--------------------------
MSR 00000407h - Pentium Pro - "MC1_MISC"
----------S00000408--------------------------
MSR 00000408h - Pentium Pro - "MC2_CTL" Machine Check Control 2
SeeAlso: MSR 00000400h,MSR 00000404h,MSR 0000040Ch
----------S00000409--------------------------
MSR 00000409h - Pentium Pro - "MC2_STATUS" Machine Check Status 2
----------S0000040A--------------------------
MSR 0000040Ah - Pentium Pro - "MC2_ADDR" Machine Check Address 2
----------S0000040B--------------------------
MSR 0000040Bh - Pentium Pro - "MC2_MISC"
----------S0000040C--------------------------
MSR 0000040Ch - Pentium II - "MC4_CTL" Machine Check Control 4
SeeAlso: MSR 000040Dh,MSR 00000400h,MSR 00000404h,MSR 00000408h
----------S0000040D--------------------------
MSR 0000040Dh - Pentium II - "MC4_STATUS" Machine Check Status 4
SeeAlso: MSR 000040Ch,MSR 000040Eh
----------S0000040E--------------------------
MSR 0000040Eh - Pentium II - "MC4_ADDR" Machine Check Address 4
SeeAlso: MSR 000040Ch,MSR 000040Dh
----------S00000410--------------------------
MSR 00000410h - Pentium Pro - "MC3_CTL" Machine Check Control 3
SeeAlso: MSR 00000400h,MSR 00000404h,MSR 0000040Ch
----------S00000411--------------------------
MSR 00000411h - Pentium Pro - "MC3_STATUS" Machine Check Status 3
----------S00000412--------------------------
MSR 00000412h - Pentium Pro - "MC3_ADDR" Machine Check Address 3
----------S00000413--------------------------
MSR 00000413h - Pentium Pro - "MC3_MISC"
----------S00001000--------------------------
MSR 00001000h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER
Size:	19 bits
Access:	Read/Write
SeeAlso: MSR 00001001h,MSR 00001002h

Bitfields for IBM 386/486 SLC Processor Operation Register:
Bit(s)	Description	(Table R0053)
 63-19	reserved
 18	(486SLC only) Low Power PLA
 17	(486SLC only) Bus Read
 16	(486SLC only) Cache Parity Generate Error
 15	enable cacheability of NPX operands
 14	enable PWI ADS
 13	enable Low Power Halt Mode (HLT instruction stops CPU clock)
 12	extended Out instruction (CPU waits for READY after any output)
 11	cache reload bit
 10	enable internal KEN# signal
 9	disable cache lock mode
 8	reserved
 7	enable cache
 6	enable DBCS
 5	enable Power Interrupt
 4	enable Flush Snooping
 3	enable Snoop Input
 2	address line A20 mask (see also #02753,#P0415)
 1	enable cache parity checking
 0	Cache Parity Error occurred
SeeAlso: #R0054,#R0055
----------S00001000--------------------------
MSR 00001000h - Pentium Pro - DEBUG REGISTER 0 
SeeAlso: MSR 00001001h"Pro",MSR 00001007h"Pro"
----------S00001001--------------------------
MSR 00001001h - IBM 386/486 SLC - CACHE REGION CONTROL REGISTER
Size:	48 bits
SeeAlso: MSR 00001000h,MSR 00001002h

Bitfields for IBM 386/486 SLC Cache Region Control Register:
Bit(s)	Description	(Table R0054)
 63-48	reserved
 47-32	extended memory cache memory limit (number of 64K blocks above 1M
	  which may be cached)
 31-16	first megabyte read-only flags (each bit represents 64K)
 15-0	first megabyte cacheable flags (each bit represents 64K)
SeeAlso: #R0053,#R0055
----------S00001001--------------------------
MSR 00001001h - Pentium Pro - DEBUG REGISTER 1
SeeAlso: MSR 00001000h"Pro",MSR 00001002h"Pro"
----------S00001002--------------------------
MSR 00001002h - IBM 386/486 SLC - PROCESSOR OPERATION REGISTER
Size:	30 bits
SeeAlso: MSR 00001000h,MSR 00001001h,MSR 00001004h

Bitfields for IBM 386/486 SLC Processor Operation Register:
Bit(s)	Description	(Table R0055)
 63-30	reserved
 29	enable External Dynamic Frequency Shift
 28	Dynamic Frequency Shift ready
 27	Dynamic Frequency Shift Mode
 26-24	clocking mode
	000 clock x1
	011 clock doubler
	100 clock tripler
 23-0	reserved
SeeAlso: #R0053,#R0054
----------S00001002--------------------------
MSR 00001002h - Pentium Pro - DEBUG REGISTER 2
SeeAlso: MSR 00001001h"Pro",MSR 00001003h"Pro"
----------S00001003--------------------------
MSR 00001003h - Pentium Pro - DEBUG REGISTER 3
SeeAlso: MSR 00001002h"Pro",MSR 00001004h"Pro"
----------S00001004--------------------------
MSR 00001004h - IBM 486BL3 - PROCESSOR CONTROL REGISTER
Size:	24 bits
SeeAlso: MSR 00001000h

Bitfields for IBM 486BL3 Processor Control Register:
Bit(s)	Description	(Table R0056)
 63-24	reserved
 23	OS/2 boot (0=DD1 hardware, 1=DD0 hardware)
 22	MOV CR0,x Decode
	0: DD0, DD1A, DD1B, DD1D hardware
	1: DD1C hardware
 21	reserved
 20	Cache Low Power (DD1 only: cache disabled when not in use)
 19	reserved
 18	NOP timing
	0: 2 cycles on DD0, 3 cycles on DD1
	1: 3 cycles on DD0, 2 cycles on DD1
 17	bus pipelining for 16-bit accesses
 16-5	reserved???
 4	MOVS split
 3	power-saving cache feature
 2	reserved
 1	enable MOV CRx decode
	(reserved on DD1B, DD1C)
 0	reserved
SeeAlso: MSR 00001000h
----------S00001004--------------------------
MSR 00001004h - Pentium Pro - DEBUG REGISTER 4 
SeeAlso: MSR 00001003h"Pro",MSR 00001005h"Pro"
----------S00001005--------------------------
MSR 00001005h - Pentium Pro - DEBUG REGISTER 5 
SeeAlso: MSR 00001004h"Pro",MSR 00001006h"Pro"
----------S00001006--------------------------
MSR 00001006h - Pentium Pro - DEBUG REGISTER 6 
SeeAlso: MSR 00001005h"Pro",MSR 00001007h"Pro"
----------S00001007--------------------------
MSR 00001007h - Pentium Pro - DEBUG REGISTER 7 
SeeAlso: MSR 00001006h"Pro",MSR 00001000h"Pro",MSR 00002000h"Pro"
----------S00002000--------------------------
MSR 00002000h - Pentium Pro - CONTROL REGISTER 0
SeeAlso: MSR 00001000h"Pro",MSR 00002002h"Pro"
----------S00002002--------------------------
MSR 00002002h - Pentium Pro - CONTROL REGISTER 2
SeeAlso: MSR 00002000h"Pro",MSR 00002003h"Pro"
----------S00002003--------------------------
MSR 00002003h - Pentium Pro - CONTROL REGISTER 3
SeeAlso: MSR 00002002h"Pro",MSR 00002004h"Pro"
----------S00002004--------------------------
MSR 00002004h - Pentium Pro - CONTROL REGISTER 4
SeeAlso: MSR 00002003h"Pro",MSR 00002000h"Pro"
----------S80000000--------------------------
MSR 80000000h - Pentium - MACHINE CHECK EXCEPTION ADDRESS
Size:	64 bits
Access:	Read
SeeAlso: MSR 00000000h,MSR 80000001h
----------S80000001--------------------------
MSR 80000001h - Pentium - MACHINE CHECK EXCEPTION TYPE
Size:	6 bits
Access:	Read
SeeAlso: MSR 00000001h,MSR 80000000h
----------S80000002--------------------------
MSR 80000002h - Pentium - (TR1) PARITY REVERSAL TEST REGISTER
Size:	14 bits
Access:	Write
SeeAlso: MSR 00000002h
----------S80000003--------------------------
MSR 80000003h - Pentium - unimplemented
SeeAlso: MSR 00000003h
----------S80000004--------------------------
MSR 80000004h - Pentium - (TR2) INSTRUCTION CACHE END BITS
Size:	4 bits
Access:	Read/Write
SeeAlso: MSR 00000004h
----------S80000005--------------------------
MSR 80000005h - Pentium - (TR3) CACHE DATA TEST REGISTER
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 00000005h
----------S80000006--------------------------
MSR 80000006h - Pentium - (TR4) CACHE TAG
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 00000006h
----------S80000007--------------------------
MSR 80000007h - Pentium - (TR5) CACHE CONTROL
Size:	15 bits
Access:	Write
SeeAlso: MSR 00000007h
----------S80000008--------------------------
MSR 80000008h - Pentium - (TR6) TLB COMMAND
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 00000008h
----------S80000009--------------------------
MSR 80000009h - Pentium - (TR7) TLB DATA
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 00000009h
----------S8000000A--------------------------
MSR 8000000Ah O - Pentium A-step - (TR8) 36-BIT TLB DATA TEST REGISTER
Size:	4 bits
SeeAlso: MSR 0000000Ah,#R0009
----------S8000000B--------------------------
MSR 8000000Bh - Pentium - (TR9) BRANCH TARGET BUFFER TAG
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 0000000Bh
----------S8000000C--------------------------
MSR 8000000Ch - Pentium - (TR10) BRANCH TARGET BUFFER TARGET
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 0000000Ch
----------S8000000D--------------------------
MSR 8000000Dh - Pentium - (TR11) BRANCH TARGET BUFFER CONTROL
Size:	12 bits
Access:	Write
SeeAlso: MSR 0000000Dh
----------S8000000E--------------------------
MSR 8000000Eh - Pentium - (TR12) NEW FEATURE CONTROL
Size:	10 bits
Access:	Write
SeeAlso: MSR 0000000Eh
----------S8000000F--------------------------
MSR 8000000Fh - Pentium - ???
Size:	1 bit???
Access:	Write
SeeAlso: MSR 0000000Fh
----------S80000010--------------------------
MSR 80000010h - Pentium - TIME STAMP COUNTER
Size:	64 bits
Access:	Read/Write
SeeAlso: MSR 00000010h
----------S80000011--------------------------
MSR 80000011h - Pentium - EVENT COUNTER SELECTION AND CONTROL
Size:	26 bits
Access:	Read/Write
SeeAlso: MSR 00000011h,MSR 80000012h,MSR 80000013h
----------S80000012--------------------------
MSR 80000012h - Pentium - EVENT COUNTER #0
Size:	40 bits
Access:	Read/Write
SeeAlso: MSR 00000012h,MSR 80000011h,MSR 80000013h
----------S80000013--------------------------
MSR 80000013h - Pentium - EVENT COUNTER #1
Size:	40 bits
Access:	Read/Write
SeeAlso: MSR 00000013h,MSR 80000011h,MSR 80000012h
----------S80000014--------------------------
MSR 80000014h - Pentium - ???
Access:	Read
SeeAlso: MSR 00000014h
----------S80000015--------------------------
MSR 80000015h - Pentium - unimplemented???
----------S80000016--------------------------
MSR 80000016h - Pentium - unimplemented???
----------S80000017--------------------------
MSR 80000017h - Pentium - unimplemented???
----------S80000018--------------------------
MSR 80000018h - Pentium - ??? (PAGING-RELATED)
Size:	4 bits???
Access:	Read
----------S80000019--------------------------
MSR 80000019h - Pentium - FLOATING POINT - LAST PREFETCHED OPCODE
Size:	11 bits
Access:	Read
Desc:	this register stores the opcode of the last floating-point opcode to
	  be prefetched by the CPU
SeeAlso: MSR 8000001Ah,MSR 8000001Bh

Bitfields for Pentium Floating-Point Opcode:
Bit(s)	Description	(Table R0057)
 63-11	reserved (0)
 10-8	low three bits of first byte of floating-point instruction
 7-0	second byte of floating-point instruction
Note:	both a standalone FWAIT and the instruction D8h 9Bh are represented
	  as 09Bh
----------S8000001A--------------------------
MSR 8000001Ah - Pentium - FLOATING POINT - LAST NON-CONTROL OPCODE
Size:	11 bits
Access:	Read
SeeAlso: MSR 80000019h,MSR 8000001Bh,#R0057
----------S8000001B--------------------------
MSR 8000001Bh - Pentium - FLOATING POINT - LAST EXCEPTION OPCODE
Size:	11 bits
Access:	Read/Write
SeeAlso: MSR 80000019h,MSR 8000001Ah,#R0057
----------S8000001C--------------------------
MSR 8000001Ch - Pentium - ???
Size:	4 bits???
Access:	Read
----------S8000001D--------------------------
MSR 8000001Dh - Pentium - PROBE MODE CONTROL REGISTER
Size:	32 bits
Access:	Read/Write

Bitfields for Probe Mode Control Register:
Bit(s)	Description	(Table R0058)
 31	(read-only) System Management Mode is active
 30-3	reserved (0)
 2	PB1 monitors breakpoint #1 matches instead of performance counter #1
 1	PB0 monitors breakpoint #0 matches instead of performance counter #0
 0	ICEBP enabled (every debug exception enters Probe Mode)
----------S8000001E--------------------------
MSR 8000001Eh - Pentium - ???
Size:	32 bits
Access:	Read/Write
Note:	this may be nothing more than a scratchpad register
SeeAlso: MSR 8000001Fh
----------S8000001F--------------------------
MSR 8000001Fh - Pentium - ???
Size:	32 bits
Access:	Read/Write
Note:	this may be nothing more than a scratchpad register
SeeAlso: MSR 8000001Eh
----------SC0000080--------------------------
MSR C0000080h - AMD K6 - EXTENDED FEATURE ENABLE REGISTER
Size:	1 bit
SeeAlso: MSR C0000081h,MSR C0000082h

Bitfields for AMD K6 Extended Feature Enable Register:
Bit(s)	Description	(Table R0059)
 63-1	reserved
 0	system call extension (SYSCALL/SYSRET) enabled
	when disabled, both instructions generate an Undefined Opcode
	  exception
Note:	CPUID 80000001h should be checked to determine whether the SYSCALL
	  extension is implemented by the processor
SeeAlso: #R0060
----------SC0000081--------------------------
MSR C0000081h - AMD K6 - SYSCALL TARGET ADDRESS
Size:	48 bits
Note:	if SYSCALL is supported (as indicated by CPUID; SYSCALL is not
	  yet implemented in current steppings of the K6), this MSR specifies
	  the address to which the SYSCALL instruction (opcode 0Fh 05h -- same
	  as 80286 LOADALL!) transfers c