msr.lst

中断列表(2) 352K

MSR 00000131h - Pentium Pro - ???
----------S0000014E--------------------------
MSR 0000014Eh - Pentium Pro - ???
----------S0000014F--------------------------
MSR 0000014Fh - Pentium Pro - ???
----------S00000150--------------------------
MSR 00000150h - Pentium Pro - ???
----------S00000151--------------------------
MSR 00000151h - Pentium Pro - ???
----------S00000154--------------------------
MSR 00000154h - Pentium Pro - ???
----------S0000015B--------------------------
MSR 0000015Bh - Pentium Pro - ???
----------S0000015F--------------------------
MSR 0000015Fh - Pentium Pro - ???
----------S00000174--------------------------
MSR 00000174h - Pentium Pro - "SYSENTER_CS" - SYSENTER target CS
----------S00000175--------------------------
MSR 00000175h - Pentium Pro - "SYSENTER_ESP" - SYSENTER target ESP
----------S00000176--------------------------
MSR 00000176h - Pentium Pro - "SYSENTER_EIP" - SYSENTER target EIP
----------S00000179--------------------------
MSR 00000179h - Pentium Pro - "MCG_CAP"
SeeAlso: MSR 0000017Ah,MSR 0000017Bh

Bitfields for Pentium Pro "MCG_CAP" register:
Bit(s)	Description	(Table R0046)
 63-8	???
 7-0	number of MCRs
----------S0000017A--------------------------
MSR 0000017Ah - Pentium Pro - "MCG_STATUS"
SeeAlso: MSR 00000179h,MSR 0000017Bh
----------S0000017B--------------------------
MSR 0000017Bh - Pentium Pro - "MCG_CTL"
SeeAlso: MSR 00000179h,MSR 0000017Ah
----------S00000186--------------------------
MSR 00000186h - Pentium Pro - "EVNTSEL0" - PERFORM. COUNTER EVENT SELECTION 0
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 000000C1h,MSR 00000187h,MSR 00000011h,MSR 00000012h

Bitfields for Pentium Pro Event Selection MSR:
Bit(s)	Description	(Table R0047)
 31-24	CMASK (counter mask)
	compare actual count for event on this clock cycle with mask; only
	  increment counter if count >= mask (count < mask if bit 23 set)
 23	invert result of CMASK condition
 22	enable counting of events
 21	reserved
 20	signal performance counter overflows via APIC input
 19	signal performance counter overflows via BP0/BP1 pin
 18	count occurrences, not duration
 17	OS (enable counting in ring 0)
 16	USER (enable counting in rings 1,2,3)
 15-8	UMASK (Unit Mask register; set to 0 to enable all count options)
 7-0	event type (see #R0048)

(Table R0048)
Values for Pentium Pro/Pentium II performance event type:
 00h-01h	documented as unused
 02h	number of store buffer forwards
 03h	number of store buffer blocks
 04h	number of store buffer drain cycles
 05h	misaligned data memory references
 06h	segment register loads
 07h-0Fh	documented as unused
 10h	executed computational FP operations
 11h	number of microcode-handled FP exceptions
 12h	number of multiplies
 13h	number of divisions
 14h	divider busy cycles
 15h-20h	documented as unused
 21h	L2 address strobes
 22h	L2 cache data bus wait cycles
 23h	L2 cache data bus transfer cycles
 24h	allocated L2-cache lines
 25h	allocated L2 modified lines
 26h	removed L2 lines
 27h	removed modified L2 lines
 28h	instruction fetches from L2 cache
 29h	loads requested from L2 cache
 2Ah	stores into L2 cache
 2Bh-2Dh	documented as unused
 2Eh	total L2 requests
 2Fh-3Fh	documented as unused
 40h	L1 Data Cache Unit load rquests
 41h	L1 DCU store requests
 42h	L1 DCU locked requests
 43h	total memory references (all types, reads+writes+internal retries)
 44h	documented as unused
 45h	L1 allocated lines
 46h	L1 allocated M-state lines
 47h	L1 evicted M-state lines
 48h	L1 outstanding miss cycles (weighted)
 49h	L1 data TLB misses
 4Ah-51h	documented as unused
 52h	(P-II) self-modifying code occurrences
 53h-5Fh	documented as unused
 60h	outstanding bus requests
 61h	number of cycles BNR pin driven
 62h	DRDY# asserted cycles
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 63h	number of cycles with LOCK asserted
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 64h	CPU receiving data cycles
 65h	burst-read transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 66h	read for ownership transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 67h	write-back transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 68h	instruction-fetch transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 69h	invalidate transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Ah	partial-write transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Bh	partial transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Ch	I/O transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Dh	deferred transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Eh	burst transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 6Fh	memory transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 70h	total of all transactions
	unit mask 20h to get total counts for ALL CPUs, 00h for this CPU only
 71h-78h	documented as unused
 79h	processor not-halted cycles
 7Ah	cycles in which HIT pin is driven
 7Bh	cycles in which HITM pin is driven
 7Ch-7Dh	documented as unused
 7Eh	bus-snoop stall cycles
 7Fh	documented as unused
 80h	instruction fetches
 81h	instruction fetch misses
 82h-84h	documented as unused
 85h	L1 instruction TLB misses
 86h	instruction-fetch stall cycles
 87h	instruction-length decoder stall cycles
 88h-A1h	documented as unused
 A2h	resource-related stall cycles
 A3h-AFh	documented as unused
 B0h	(P-II) MMX instructions executed
 B1h	(P-II) saturated arithmetic instructions executed
 B2h	(P-II) MMX uOPs executed on Port #0--3
 B3h	(P-II) MMX instructions
	unit mask selects type(s): 01h packed multiply, 02h packed shift,
	  04h pack operations, 08h unpack operations, 10h packed logical,
	  20h packed arithmetic
 B4h-BFh	documented as unused
 C0h	retired instructions
 C1h	retired FLOPs
 C2h	retired uOPs
 C3h	documented as unused
 C4h	retired branch predictions
 C5h	retired mispredicted branches
 C6h	total cycles with interrupts disabled
 C7h	total cycles with interrupts disabled and interrupt(s) pending
 C8h	received hardware interrupts
 C9h	retired taken branches
 CAh	retired taken mispredicted branches
 CBh	documented as unused
 CCh	(P-II) transitions between FP and MMX states
	unit mask: 00h = from MMX to FP, 01h = from FP to MMX
 CDh	(P-II) SIMD assists (EMMS instructions executed)
 CEh	(P-II) MMX instructions retired
 CFh	(P-II) saturated arithmetic instructions retired
 D0h	decoded instructions
 D1h	documented as unused
 D2h	partial stall cycles or events
 D3h	documented as unused
 D4h	(P-II) segment rename stalls
	set unit mask to sum of: 01h for ES, 02h for DS, 04h for FS, 08h for GS
 D5h	(P-II) segment renames (unit mask as for D4h)
 D6h	(P-II) retired segment renames
 D7h-DFh	documented as unused
 E0h	decoded branch instructinos
 E1h	documented as unused
 E2h	BTB misses
 E3h	documented as unused
 E4h	bogus branches (predictions generated for non-branch instructions)
 E5h	documented as unused
 E6h	number of times BACLEAR asserted (number of static branch predictions)
 E7h-FFh	documented as unused
SeeAlso: #R0047
----------S00000187--------------------------
MSR 00000187h - Pentium Pro - "EVNTSEL1" - PERFORM. COUNTER EVENT SELECTION 1
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR 000000C2h,MSR 00000186h,#R0047,MSR 00000011h,MSR 00000013h,#R0047
----------S000001D3--------------------------
MSR 000001D3h - Pentium Pro - ???
----------S000001D9--------------------------
MSR 000001D9h - Pentium Pro, PentiumII - "DEBUGCTLMSR" DEBUGGING CONTROL
Size:	16 bits

Bitfields for Pentium Pro Debugging Control MSR:
Bit(s)	Description	(Table R0049)
 63-16	reserved
 15	enable execution trace messages
 14	enable execution trace messages
 13-7	reserved
 6	enable execution trace messages
 5	performance monitor/Breakpoint pins
 4	performance monitor/Breakpoint pins
 3	performance monitor/Breakpoint pins
 2	performance monitor/Breakpoint pins
 1	Branch Trap Flag
 0	enable Last Branch records (see MSR 000001DBh,MSR 000001DCh)
----------S000001DB--------------------------
MSR 000001DBh - Pentium Pro, PentiumII - "LASTBRANCHFROMIP"
Desc:	stores the address from which a branch was last taken
SeeAlso: MSR 000001DCh,MSR 000001DDh
----------S000001DC--------------------------
MSR 000001DCh - Pentium Pro, PentiumII - "LASTBRANCHTOIP"
Desc:	stores the destination address of the last taken branch instruction
SeeAlso: MSR 000001DBh,MSR 000001DEh
----------S000001DD--------------------------
MSR 000001DDh - Pentium Pro, PentiumII - "LASTINTFROMIP"
Desc:	stores the address at which an interrupt last occurred
SeeAlso: MSR 000001DBh,MSR 000001DEh
----------S000001DE--------------------------
MSR 000001DEh - Pentium Pro, PentiumII - "LASTINTTOIP"
Desc:	stores the address to which the last interrupt caused a branch
SeeAlso: MSR 000001DCh,MSR 000001DDh
----------S000001E0--------------------------
MSR 000001E0h - Pentium Pro - "ROB_CR_BKUPTMPDR6"
Size:	>= 3 bits

Bitfields for Pentium Pro MSR 000001E0h:
Bit(s)	Description	(Table R0050)
 63-3	???
 2	Fast String Enable (default is enabled)
 1-0	reserved
Note:	if bit 2 is set, REP MOVS moves 64 bits each clock cycle if both source
	  and target are QWORD-aligned
----------S00000200--------------------------
MSR 00000200h - Pentium Pro - "MTRRphysBase0"
SeeAlso: MSR 000000FEh,MSR 00000201h,MSR 00000202h
----------S00000201--------------------------
MSR 00000201h - Pentium Pro - "MTRRphysMask0"
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000202h
----------S00000202--------------------------
MSR 00000202h - Pentium Pro - "MTRRphysBase1"
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000203h
----------S00000203--------------------------
MSR 00000203h - Pentium Pro - "MTRRphysMask1"
SeeAlso: MSR 000000FEh,MSR 00000201h,MSR 00000202h
----------S00000204--------------------------
MSR 00000204h - Pentium Pro - "MTRRphysBase2"
----------S00000205--------------------------
MSR 00000205h - Pentium Pro - "MTRRphysMask2"
----------S00000206--------------------------
MSR 00000206h - Pentium Pro - "MTRRphysBase3"
----------S00000207--------------------------
MSR 00000207h - Pentium Pro - "MTRRphysMask3"
----------S00000208--------------------------
MSR 00000208h - Pentium Pro - "MTRRphysBase4"
----------S00000209--------------------------
MSR 00000209h - Pentium Pro - "MTRRphysMask4"
----------S0000020A--------------------------
MSR 0000020Ah - Pentium Pro - "MTRRphysBase5"
----------S0000020B--------------------------
MSR 0000020Bh - Pentium Pro - "MTRRphysMask5"
----------S0000020C--------------------------
MSR 0000020Ch - Pentium Pro - "MTRRphysBase6"
----------S0000020D--------------------------
MSR 0000020Dh - Pentium Pro - "MTRRphysMask6"
----------S0000020E--------------------------
MSR 0000020Eh - Pentium Pro - "MTRRphysBase7"
----------S0000020F--------------------------
MSR 0000020Fh - Pentium Pro - "MTRRphysMask7"
----------S00000250--------------------------
MSR 00000250h - Pentium Pro - "MTRRfix64K_00000"
Desc:	control the 64K region from 00000h to 0FFFFh
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000258h
----------S00000258--------------------------
MSR 00000258h - Pentium Pro - "MTRRfix16K_80000"
Desc:	control the 16K region from 80000h to 83FFFh
SeeAlso: MSR 000000FEh,MSR 00000250h,MSR 00000259h
----------S00000259--------------------------
MSR 00000259h - Pentium Pro - "MTRRfix16K_A0000"
Desc:	control the 16K region from A0000h to A3FFFh
----------S00000268--------------------------
MSR 00000268h - Pentium Pro - "MTRRfix4K_C0000"
Desc:	control the 4K region from C0000h to C0FFFh
----------S00000269--------------------------
MSR 00000269h - Pentium Pro - "MTRRfix4K_C8000"
Desc:	control the 4K region from C8000h to C8FFFh
----------S0000026A--------------------------
MSR 0000026Ah - Pentium Pro - "MTRRfix4K_D0000"
Desc:	control the 4K region from D0000h to D0FFFh
----------S0000026B--------------------------
MSR 0000026Bh - Pentium Pro - "MTRRfix4K_D8000"
Desc:	control the 64K region from D8000h to D8FFFh
----------S0000026C--------------------------
MSR 0000026Ch - Pentium Pro - "MTRRfix4K_E0000"
Desc:	control the 64K region from E0000h to E0FFFh
----------S0000026D--------------------------
MSR 0000026Dh - Pentium Pro - "MTRRfix4K_E8000"
Desc:	control the 64K region from E8000h to E8FFFh
----------S0000026E--------------------------
MSR 0000026Eh - Pentium Pro - "MTRRfix4K_F0000"
Desc:	control the 64K region from F0000h to F0FFFh
----------S0000026F--------------------------
MSR 0000026Fh - Pentium Pro - "MTRRfix4K_F8000"
Desc:	control the 64K region from F8000h to F8FFFh
----------S00000277--------------------------
MSR 00000277h - Pentium Pro - Page Attribute Table
----------S00000280--------------------------
MSR 00000280h - PentiumII - ???
----------S000002FF--------------------------
MSR 000002FFh - Pentium Pro - "MTRRdefType" - DEFAULT MEMORY TYPE
Note:	this MSR sets the memory type to use for any range not claimed by one
	  of the other MTRRs
SeeAlso: MSR 000000FEh,MSR 00000200h,MSR 00000250h

Bitfields for Pentium Pro MSR 000002FFh:
Bit(s)	Description	(Table R0051)
 63-12	reserved
 11	"MTRRenable" enable Memory Type Register registers
 10	Fixed MTRR enable
 9-3	reserved
 2-0	default memory type
----------S00000400--------------------------
MSR 00000400h - Pentium Pro - "MC0_CTL" Machine Check Control 0
SeeAlso: MSR 00000401h,MSR 00000402h,MSR 00000404h,MSR 0000410h
----------S00000401--------------------------
MSR 00000401h - Pentium Pro - "MC0_STATUS" Machine Check Status 0
SeeAlso: MSR 00000400h,MSR 00000403h

Bitfields for Pentium Pro Machine Check Status:
Bit(s)	Description	(Table R0052)
 63	"MC_STATUS_V"
 62	"MC_STATUS_O"
 61	"MC_STATUS_UC"
 60	"MC_STATUS_EN"
 59	"MC_STATUS_MISCV"
 58	"MC_STATUS_ADDRV"
 57	"MC_STATUS_DAM"
 56-32	reserved
 31-16	"MC_STAT_MSCOD"
 15-0	"MC_STAT_MACCOD"
----------S00000402--------------------------
MSR 00000402h - Pentium Pro - "MC0_ADDR" Machine Check Address 0
SeeAlso: MSR 00000400h,MSR 00000403h