msr.lst

中断列表(2) 352K

 31-12	reserved (0)
 11	page cache disable
 10	page write-through
 9-0	page frame address
SeeAlso: #R0024,#R0030,#R0033

Bitfields for Am5k86 4M TLB linear tag:
Bit(s)	Description	(Table R0033)
 31-15	reserved (0)
 14	global valid bit
 13	TLB entry is dirty
 12	user/supervisor
 11	read/write
 10	entry is valid
 9-0	tag (bits 31-22 of address)
SeeAlso: #R0024,#R0031,#R0032

Bitfields for Am5k86 data cache physical tag:
Bit(s)	Description	(Table R0034)
 31-23	reserved (0)
 22-21	MESI status
	00 invalid
	01 shared
	10 modified
	11 exclusive
 20-0	tag (bits 31-11 of physical address)
SeeAlso: #R0024,#R0035

Bitfields for Am5k86 code cache physical tag:
Bit(s)	Description	(Table R0035)
 31-21	reserved (0)
 20	valid
 19-0	tag (bits 31-12 of physical address)
SeeAlso: #R0024,#R0034
----------S00000083--------------------------
MSR 00000083h - AMD Am5k86 (AMD-K5) - HARDWARE CONFIGURATION REGISTER
Size:	8 bits
SeeAlso: MSR 00000082h

Bitfields for AMD Am5k86 (AMD-K5) Hardware Configuration Register:
Bit(s)	Description	(Table R0036)
 63-8	reserved
 7	disable data cache
 6	disable instruction cache
 5	disable branch prediction
 4	enable write allocation (stepping 4 and higher only)
 3-1	debug control
	000 off
	001 enable branch trace (requires bit 5 set as well)
	100 enable Probe Mode on debug trap
	other reserved
 0	disable Stopping Processor Clock in Halt and Stop Grant states
SeeAlso: #R0023
----------S00000085--------------------------
MSR 00000085h - AMD-K5 - WRITE ALLOCATE TOP-OF-MEMORY AND CONTROL REGISTER
Note:	this MSR is supported on K5 models 1/2/3 stepping 4 and higher only
SeeAlso: MSR 00000086h
!!!amd\21062e.pdf p.95
----------S00000086--------------------------
MSR 00000086h - AMD-K5 - WRITE ALLOCATE PROGRAMMABLE MEMORY RANGE REGISTER
Note:	this MSR is supported on K5 models 1/2/3 stepping 4 and higher only
SeeAlso: MSR 00000085h
----------S00000088--------------------------
MSR 00000088h - Pentium Pro, PentiumII - "BBL_CR_D0" CHUNK 0 DATA REGISTER
Note:	this register is used to read from and write to L2 cache
SeeAlso: MSR 00000089h,MSR 0000008Ah,MSR 00000116h
----------S00000089--------------------------
MSR 00000089h - Pentium Pro, PentiumII - "BBL_CR_D1" CHUNK 1 DATA REGISTER
Note:	this register is used to read from and write to L2 cache
SeeAlso: MSR 00000088h,MSR 0000008Ah,MSR 00000116h
----------S0000008A--------------------------
MSR 0000008Ah - Pentium Pro, PentiumII - "BBL_CR_D2" CHUNK 2 DATA REGISTER
Note:	this register is used to read from and write to L2 cache
SeeAlso: MSR 00000088h,MSR 00000089h,MSR 00000116h
----------S0000008B--------------------------
MSR 0000008Bh - Pentium Pro - "BIOS_SIGN" BIOS UPDATE SIGNATURE
Size:	64 bits
Access:	Read/Write
Desc:	used to determine which (if any) microcode update has been loaded into
	  the CPU
Notes:	whenever a microcode update is loaded, the PentiumPro modifies the
	  operation of the CPUID instruction to store both the standard CPUID
	  model information and a 32-bit microcode update ID into this MSR; if
	  no microcode update has been loaded, the MSR remains unchanged
	  (it is normally cleared to 0 before using CPUID to test for updates)
	the low 32 bits of this register (if modified by CPUID) contains the
	  standard model/stepping information, while the high 32 bits contain
	  the microcode update ID
SeeAlso: MSR 00000079h
----------S0000008B--------------------------
MSR 0000008Bh - PentiumII - "BBL_CR_D3" CHUNK 3 DATA REGISTER
Notes:	this register is used to read from and write to L2 cache
	whether this MSR is the BIOS update signature or L2 data depends on
	  the usage model
SeeAlso: MSR 00000088h,MSR 00000089h,MSR 00000116h
----------S000000AE--------------------------
MSR 000000AEh - Pentium Pro - ???
----------S000000C1--------------------------
MSR 000000C1h - Pentium Pro - "PERFCTR0" PERFORMANCE COUNTER REGISTER 0
Note:	the performance measure counted by this MSR is set through MSR 0186h
SeeAlso: MSR 000000C2h,MSR 00000012h,MSR 00000186h
----------S000000C2--------------------------
MSR 000000C2h - Pentium Pro - "PERFCTR1" PERFORMANCE COUNTER REGISTER 1
Note:	the performance measure counted by this MSR is set through MSR 0187h
SeeAlso: MSR 000000C1h,MSR 00000013h,MSR 00000187h
----------S000000FE--------------------------
MSR 000000FEh - Pentium Pro - "MTRRcap" MEMORY TYPE RANGE REGISTER CAPABILITIES
Desc:	determine how many and what type of Memory Type Range Registers are
	  implemented
SeeAlso: MSR 00000200h,MSR 00000250h,MSR 000002FFh

Bitfields for Pentium Pro "MTRRcap" register:
Bit(s)	Description	(Table R0037)
 63-8	???
 7-0	number of Memory Type Range Registers (at MSR 02xxh)
----------S00000107--------------------------
MSR 00000107h - Centaur (IDT) WinChip C6 - Feature Control Register #1
Size:	30 bits
SeeAlso: MSR 00000108h,MSR 00000109h

Bitfields for Centaur (IDT) WinChip C6 Feature Control Register #1:
Bit(s)	Description	(Table R0038)
 61-31	reserved
 30	enable MOV TRx instructions
 29	disable CPUID instruction
 28	don't use alternative "divide 5 by 2" EFLAGS
	0 = use Centaur (IDT) flags
	1 = use Intel flags
 27-26	reserved
 25-22	stepping ID
 21-17	reserved
 16	enable return stack (default)
 15	disable bus pipelining #NA response
 14	disable data cache
 13	disable instruction cache
 12	reserved
 11	disable page directory cache
 10	reserved
 9	enable MMX instructions (default)
 8	enable data cache updates for PDE/PTE
 7	disable check for self-modifying code
 6	enable linear burst mode
 5	disable #STPCLK support
 4	disable machine check exception
 3	disable power management
 2	enable #MC for internal errors
 1	set CPUID feature flag for CMPXCHG8 instruction
 0	reserved
SeeAlso: #R0039,#R0040
----------S00000108--------------------------
MSR 00000108h - Centaur (IDT) WinChip C6 - Feature Control Register #2
Size:	64 bits
SeeAlso: MSR 00000107h,MSR 00000109h

Bitfields for Centaur (IDT) WinChip C6 Feature Control Register #2:
Bit(s)	Description	(Table R0039)
 63-32	last four bytes of CPUID vendor ID string (see also #R0040)
 31-15	reserved
 14	use alternative CPUID vendor string
 13-12	reserved
 11-8	CPUID family
 7-4	CPUID model
 3-0	reserved
SeeAlso: #R0038,#R0039
----------S00000109--------------------------
MSR 00000109h - Centaur (IDT) WinChip C6 - Feature Control Register #3
Size:	30 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000108h

Bitfields for Centaur (IDT) WinChip C6 Feature Control Register #3:
Bit(s)	Description	(Table R0040)
 63-32	first four bytes of CPUID vendor ID string
 31-0	middle four bytes of CPUID vendor ID string
SeeAlso: #R0039
----------S00000110--------------------------
MSR 00000110h - Centaur (IDT) WinChip C6 - Memory Configuration Register #0
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000111h,MSR 00000117h"Centaur"

Bitfields for Centaur (IDT) WinChip C6 Memory Configuration Register:
Bit(s)	Description	(Table R0041)
 63-44	base address of memory region
 43-32	reserved
 31-12	memory region mask
	(region is hit if (base AND address) == (mask AND address))
 11-5	reserved
 4-3	memory write order
	00 strong ordering
	01 weak for string
	10 weak for stack
	11 weak ordering for all writes
 2	enable write merging for stack writes
 1	enable write merging for string writes
 0	enable write merging for other writes
SeeAlso: #R0045
----------S00000111--------------------------
MSR 00000111h - Centaur (IDT) WinChip C6 - Memory Configuration Register #1
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000110h,MSR 00000112h,#R0041
----------S00000112--------------------------
MSR 00000112h - Centaur (IDT) WinChip C6 - Memory Configuration Register #2
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000111h,MSR 00000113h,#R0041
----------S00000113--------------------------
MSR 00000113h - Centaur (IDT) WinChip C6 - Memory Configuration Register #3
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000112h,MSR 00000114h,#R0041
----------S00000114--------------------------
MSR 00000114h - Centaur (IDT) WinChip C6 - Memory Configuration Register #4
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000113h,MSR 00000115h,#R0041
----------S00000115--------------------------
MSR 00000115h - Centaur (IDT) WinChip C6 - Memory Configuration Register #5
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000114h,MSR 00000116h"Centaur",#R0041
----------S00000116--------------------------
MSR 00000116h - PentiumII - "BBL_CR_ADDR" - SET L2 CACHE ADDRESS
Size:	32 bits
SeeAlso: MSR 00000088h,MSR 00000118h"PentiumII"

Bitfields for PentiumII "BBL_CR_ADDR":
Bit(s)	Description	(Table R0042)
 31-3	cache address bits 31-3 (docs say 35-3!)
 2-0	reserved (0) 
----------S00000116--------------------------
MSR 00000116h - Centaur (IDT) WinChip C6 - Memory Configuration Register #6
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000115h,MSR 00000117h"Centaur",#R0041
----------S00000117--------------------------
MSR 00000117h - Centaur (IDT) WinChip C6 - Memory Configuration Register #7
Size:	64 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000110h,MSR 00000116h"Centaur",#R0041
----------S00000118--------------------------
MSR 00000118h - PentiumII - "BBL_CR_DECC" READ/WRITE L2 CACHE ECC BITS
Size:	8 bits
SeeAlso: MSR 00000088h,MSR 00000116h"PentiumII",MSR 00000119h
----------S00000119--------------------------
MSR 00000119h - PentiumII - "BBL_CR_CTL"
SeeAlso: MSR 00000118h,MSR 0000011Ah

Bitfields for PentiumII "BBL_CR_CTL":
Bit(s)	Description	(Table R0043)
 63-19	reserved
 18	use supplied ECC
 17	reserved
 16	L2 hit
 15-14	reserved
 13-12	state from L2 entry
	00 invalid
	01 shared
	10 exclusive
	11 modified
 11-10	way number from L2 cache
 9-8	way number to L2
 7	reserved
 6-5	state to L2 entry (as for bits 13-12)
 4-0	L2 command
	00010 read L2 control register
	00011 write L2 control register
	010mm tag write with data read
	01100 data read with LRU update
	01110 tag read with data read
	01111 tag inquire
	100mm tag write
	('mm' = MESI state, coded as for bits 13-12)
----------S0000011A--------------------------
MSR 0000011Ah - PentiumII - "BBL_CR_TRIG" TRIGGER CACHE CONFIGURATION CYCLE
Note:	a write (must write 00000000h!) to this MSR triggers a cache
	  configuration access cycle
SeeAlso: MSR 00000088h,MSR 00000118h,MSR 0000011Bh
----------S0000011B--------------------------
MSR 0000011Bh - PentiumII - "BBL_CR_BUSY" CHECK IF CACHE CONFIG IN PROGRESS
Size:	1 bit
Access:	Read-Only
Note:	if bit 0 is set, an L2 cache configuration access command is in
	  progress
SeeAlso: MSR 00000088h,MSR 00000118h,MSR 0000011Ah
----------S0000011E--------------------------
MSR 0000011Eh - Pentium II - "BBL_CR_CTL3" L2 CACHE CONTROL REGISTER 3
SeeAlso: MSR 00000088h,MSR 00000116h,MSR 0000011Ah,MSR 0000011Bh

Bitfields for Pentium II L2 cache control:
Bit(s)	Description	(Table R0044)
 63-26	reserved
 25	(read-only) cache bus fraction
 24	reserved
 23	(read-only) L2 hardware disable
 22-20	supported L2 physical address range
	000  512M
	001    1G
	010    2G
	011    4G
	100    8G
	101   16G
	110   32G
	111   64G
 19	reserved
 18	enable cache state error checking
 17-13	cache size per bank
	00001 256K
	00010 512K
	00100	1M
	01000	2M
	10000	4M
 12-11	(read-only) number of L2 banks
 10-9	(read-only) L2 associativity
	00 direct-mapped
	01 2-way associative
	10 4-way associative
	11 reserved
 8	L2 cache enabled
 7	CRTN parity checking enabled
 6	address parity checking enabled
 5	enable ECC testing of L2 cache memory
 4-1	L2 cache latency
 0	L2 has been configured
----------S00000120--------------------------
MSR 00000120h - Centaur (IDT) WinChip C6 - Memory Config Register Control
Size: 25 bits
Access:	Write-Only
SeeAlso: MSR 00000107h,MSR 00000110h,MSR 00000117h

Bitfields for Centaur (IDT) WinChip C6 Memory Configuration Control Register:
Bit(s)	Description	(Table R0045)
 63-25	reserved
 24-20	reserved (1)
 19-5	reserved
 4	enable weak write ordering
 3-2	write merging for string writes
	00 forward combining
	01 forward/overlapped
	10 forward/reverse
	11 forward/reverse/overlap
 1-0	write merging for non-stack/non-string writes
	00 forward combining
	01 forward/overlapped
	10 forward/reverse
	11 forward/reverse/overlap
SeeAlso: #R0041
----------S00000131--------------------------