msr.lst

中断列表(2) 352K

 5-0	event type for counter 0 (see #R0017)
SeeAlso: #R0016

Bitfields for IDT WinChip C6 Event Counter Control:
Bit(s)	Description	(Table R0016)
 63-24	reserved
 23-16	counter 1 control (see #R0018)
 15-8	reserved
 7-0	counter 0 control (see #R0018)
SeeAlso: #R0015

(Table R0017)
Values for Pentium/6x86MX Event Counter event type:
 00h	data read
 01h	data write
 02h	data TLB miss
 03h	data read miss
 04h	data write miss
 05h	write hit to Modified/Exclusive cache line
 06h	data cache lines written back
 07h	external data cache snoops
 08h	external data cache snoop hits
 09h	simultaneous memory accesses in both pipes
 0Ah	data bank access conflict between U and V pipes
 0Bh	misaligned data memory or I/O references
 0Ch	code read
 0Dh	code TLB miss
 0Eh	code cache miss
 0Fh	any segment register load
 10h	(Pentium only) segment descriptor cache accessed
 11h	(Pentium only) segment descriptor cache hit
 12h	any branch
 13h	BTB hit
 14h	taken branch / BTB hit
 15h	pipeline flushes
 16h	total instructions executed
 17h	instruction executed in V pipe
 18h	bus utilization
 19h	pipeline stalled by write backups
 1Ah	pipeline stalled by data memory read
 1Bh	pipeline stalled by write to Modified/Exclusive cache line
 1Ch	locked bus cycle
 1Dh	I/O cycle
 1Eh	non-cacheable memory references
 1Fh	pipeline stalled by Address Generation Interlock
 20h	source/destination conflict
 21h	(undoc) decoding stalls (could only decode one instruction in a
	  particular clock cycle, and that instruction was potentially
	  pairable; i.e. if the following instruction could have executed in
	  the V pipe, it didn't because it wasn't decoded in time)
 22h	floating-point operations
 23h	Breakpoint 0 match
 24h	Breakpoint 1 match
 25h	Breakpoint 2 match
 26h	Breakpoint 3 match
 27h	hardware interrupt
 28h	data read or data write
 29h	data read/write miss
---Pentium---
 2Ah-3Fh reserved
---PentiumMMX---
 2Ah	bus ownership latency (counter 0, duration) or
	bus ownership transfers (counter 1)
 2Bh	MMX instructions executed in U pipe (counter 0) or V pipe (counter 1)
 2Ch	cache M-state line sharing (counter 0) or
	cache line sharing (counter 1)
 2Dh	EMMS instructions executed (counter 0) or
	transitions between MMX/FP (counter 1)
 2Eh	bus use due to processor activity (counter 0, duration) or
	writes to non-cacheable memory (counter 1)
 2Fh	saturating MMX instructions executed (counter 0) or
	saturations performed (counter 1)
 30h	number of cycles not in HLT state (counter 0) or
	number of cycles in HLT state (counter 1)
 31h	MMX instruction data reads (counter 0) or
	MMX instruction data read misses
 32h	floating-point stalls (counter 0) or taken branches (counter 1)
 33h	D1 starvation and FIFO is empty (counter 0) or
	D1 starvation and only one instruction in FIFO (counter 1)
 34h	MMX instruction data writes (counter 0) or
	MMX instruction data write misses (counter 1)
 35h	pipeline flushes due to wrong branch prediction (counter 0) or
	pl. flushes due to wrong branch pred. resolved in WB stage (counter 1)
 36h	misaligned data memory reference on MMX instruction (counter 0) or
	pipeline stalled waiting for MMX instruction data mem read (counter 1)
 37h	returns, predicted incorrectly or not at all (counter 0) or
	total returns predicted (counter 1)
 38h	clocks MMX instruction multiply unit interlock (counter 0) or
	clocks MOVD/MOVQ store stall (counter 1)
 39h	returns (counter 0 only)
 3Ah	BTB false entries (counter 0) or
	BTB prediction miss on not-taken branch (counter 1)
 3Bh	clocks MMX instruction stalled due to full write buffers (counter 0) or
	clocks stalled on MMX instruction write to E or M line (counter 1)
---6x86MX---
 2Ah	reserved
 2Bh	MMX instructions executed in X pipe (counter 0) or Y pipe (counter 1)
 2Ch	reserved
 2Dh	EMMS instructions executed (counter 0) or
	transitions between MMX/FP (counter 1)
 2Eh	reserved
 2Fh	saturating MMX instructions executed (counter 0) or
	saturations performed (counter 1)
 30h	reserved
 31h	MMX instruction data reads (counter 0 only)
 32h	taken branches (counter 1 only)
 33h-36h reserved
 37h	returns, predicted incorrectly or not at all (counter 0) or
	total returns predicted (counter 1)
 38h	clocks MMX instruction multiply unit interlock (counter 0) or
	clocks MOVD/MOVQ store stall (counter 1)
 39h	returns (counter 0) or return stack buffer overflows (counter 1)
 3Ah	BTB false entries (counter 0) or
	BTB prediction miss on not-taken branch (counter 1)
 3Bh	clocks MMX instruction stalled due to full write buffers (counter 0) or
	clocks stalled on MMX instruction write to E or M line (counter 1)
 3Ch-3Fh reserved
 40h	L2 TLB misses (code or data)
 41h	L2 TLB data miss
 42h	L2 TLB code miss
 43h	L1 TLB miss (code or data)
 44h	TLB flushes
 45h	TLB page invalidations
 46h	TLB page invalidations which hit
 47h	reserved
 48h	instructions decoded
 49h-7Fh reserved
SeeAlso: #R0015,#R0018

(Table R0018)
Values for IDT WinChip C6 event:
 00h	internal clocks
 01h	valid cycles reaching writebacks
 02h	x86 instructions
 47h	data read cache misses
 4Ah	data write cache misses
 63h	instruction fetch cache miss
SeeAlso: #R0016,#R0017
----------S00000012--------------------------
MSR 00000012h - Pentium, Cyrix 6x86MX - EVENT COUNTER #0
Size:	40 bits
Access:	Read/Write
Note:	also supported by Cyrix 6x86MX and Centaur (IDT) WinChip C6
SeeAlso: MSR 00000011h,MSR 00000013h,MSR 80000012h,MSR 000000C1h
----------S00000013--------------------------
MSR 00000013h - Pentium, Cyrix 6x86MX - EVENT COUNTER #1
Size:	40 bits
Access:	Read/Write
Note:	also supported by Cyrix 6x86MX and Centaur (IDT) WinChip C6
SeeAlso: MSR 00000011h,MSR 00000012h,MSR 80000013h,MSR 000000C2h
----------S00000014--------------------------
MSR 00000014h - Pentium P54C - bug?
Note:	returns 0 on all reads and ignores any writes for P54C processors with
	  CPUID values <= 0524h, rather than causing an exception; possibly due
	  to a microcode bug
----------S00000017--------------------------
MSR 00000017h - Pentium Pro - ???
----------S00000018--------------------------
MSR 00000018h - Pentium Pro - ???
----------S0000001B--------------------------
MSR 0000001Bh - Pentium Pro, PentiumII - APIC BASE ADDRESS
SeeAlso: MEM FEE00000h

Bitfields for Pentium Pro/PentiumII MSR 0000001Bh:
Bit(s)	Description	(Table R0019)
 63-32	reserved
 31-12	APIC base address bits 31-12
 11	APIC global enable (can not be cleared except through hard reset)
 10-9	reserved
 8	this is the BootStrap Processor
 7-0	reserved
----------S00000021--------------------------
MSR 00000021h - Pentium II - ???
----------S0000002A--------------------------
MSR 0000002Ah - Pentium Pro - "EBL_CR_POWERON"
Size:	32 bits
Access:	Read/write

Bitfields for Pentium Pro MSR 0000002Ah:
Bit(s)	Description	(Table R0020)
 31-27	reserved
 26	(read-only) Low Power enable
 25	reserved
 24-22	(read-only) clock frequency ratio (see #R0021)
 21-20	(read-only) symmetric arbitration ID
 19-18	???
 17-16	(read-only) APIC cluster ID
 15	(read-only) FRC [Funtional Redundancy Checking] mode enabled
 14	(read-only) Power-on Reset Vector at 1M instead of 4G
 13	(read-only) IN Order Queue depth is 1 instead of 8
 12	(read-only) BINIT# observation enabled
 11	???
 10	(read-only) AERR# observation enabled
 9	Execute-BIST enabled
 8	output tri-state enabled
 7	disable BINIT# drive
 6	disable BERR# for initiator internal errors
 5	reserved
 4	disable BERR# for initiator bus requests
 3	disable AERR# drive
 2	disable response error checking
 1	disable data error checking
 0	data bus uses ECC instead of parity

(Table R0021)
Values for Pentium Pro/PentiumII clock multiplier:
 0	x2
 1	x4
 2	x3
 4	x2.5
 6	x3.5
 15	x2
SeeAlso: #R0020
----------S00000032--------------------------
MSR 00000032h - Pentium Pro - ???
----------S00000033--------------------------
MSR 00000033h - Pentium Pro, PentiumII - "TEST_CTL" TEST CONTROL REGISTER
SeeAlso: 32 bits

Bitfields for Pentium Pro MSR 0033h:
Bit(s)	Description	(Table R0022)
 31	(step sB1 and later) disable LOCK# for locked transactions which
	  are split across a cache line boundary
 30	(step sB1 and later) disable Instruction Streaming buffers
	--used to work around sB1 errata 58 and 59
 29-0	reserved
----------S00000034--------------------------
MSR 00000034h - Pentium Pro - ???
----------S0000003A--------------------------
MSR 0000003Ah - Pentium Pro - ???
----------S0000003B--------------------------
MSR 0000003Bh - PentiumII - ???
----------S00000050--------------------------
MSR 00000050h - Pentium Pro - ???
----------S00000051--------------------------
MSR 00000051h - Pentium Pro - ???
----------S00000052--------------------------
MSR 00000052h - Pentium Pro - ???
----------S00000053--------------------------
MSR 00000053h - Pentium Pro - ???
----------S00000054--------------------------
MSR 00000054h - Pentium Pro - ???
----------S00000079--------------------------
MSR 00000079h - Pentium Pro, PentiumII - BIOS UPDATE TRIGGER
Size:	32 bits
Access:	Write
Desc:	writing the linear address of a microcode update block (see #00533)
	  to this MSR cause the CPU to initiate a microcode load
SeeAlso: INT 15/AX=D042h/BL=01h,MSR 0000008Bh
----------S00000082--------------------------
MSR 00000082h - AMD Am5k86 (AMD-K5) - ARRAY ACCESS REGISTER
Size:	64 bits
Note:	EDX remains unchanged after an RDMSR to simplify multiple accesses
SeeAlso: MSR 00000083h

Bitfields for AMD Am5k86 (AMD-K5) Array Access Register:
Bit(s)	Description	(Table R0023)
 63-40	pointer within array specified below
 39-32	array identifier (see #R0024)
 31-0	array data
SeeAlso: #R0036

(Table R0024)
Values for AMD Am5k86 Array Pointer:
 E0h	data cache (data)
 E1h	data cache (linear tag) (see #R0025)
 E4h	code cache (instruction) (see #R0026)
 E5h	code cache (linear tag) (see #R0027)
 E6h	code cache (valid bits) (see #R0028)
 E7h	code cache (branch-prediction bits) (see #R0029)
 E8h	4K TLB (page) (see #R0030)
 E9h	4K TLB (linear tag) (see #R0031)
 EAh	4M TLB (page) (see #R0032)
 EBh	4M TLB (linear tag) (see #R0033)
 ECh	data cache (physical tag) (see #R0034)
 EDh	code cache (physical tag) (see #R0035)
SeeAlso: #R0023

Bitfields for AMD AmK586 data cache linear tag:
Bit(s)	Description	(Table R0025)
 31-26	reserved (0)
 25	cache line is dirty
 24	user/supervisor
 23	read/write
 22	0
 21	linear address valid
 20-0	tag
SeeAlso: #R0024,#R0034

Bitfields for AMD Am5k86 code cache instruction:
Bit(s)	Description	(Table R0026)
 31-26	reserved (0)
 25	start bit 1
 24	end bit 1
 23	opcode bit 1
 22-21	map (ROPs/MROM) 1
 20-13	byte 1
 12	start bit 0
 11	end bit 0
 10	opcode bit 0
 9-8	map (ROPs/MROM) 0
 7-0	byte 0
SeeAlso: #R0024,#R0027,#R0035

Bitfields for Am5k86 code cache linear tag:
Bit(s)	Description	(Table R0027)
 31-20	reserved (0)
 19-0	bits 31-12 of linear address
SeeAlso: #R0024,#R0026,#R0028,#R0035

Bitfields for Am5k86 code cache valid bits:
Bit(s)	Description	(Table R0028)
 31-18	reserved (0)
 17	linear tag is valid
 16	user/supervisor
 15-0	bitmask of valid bytes
SeeAlso: #R0024,#R0026,#R0035

Bitfields for Am5k86 code cache branch prediction bits:
Bit(s)	Description	(Table R0029)
 31-19	reserved (0)
 18	predicted branch taken
 17-14	offset of last byte of predicted branch instruction within block
 13-12	predicted target column
 11-4	predicted target index
 3-0	target byte
SeeAlso: #R0024

Bitfields for Am5k86 4K TLB page:
Bit(s)	Description	(Table R0030)
 31-22	reserved (0)
 21	page cache disable
 20	page write-through
 19-0	page frame address
SeeAlso: #R0024,#R0031,#R0032

Bitfields for Am5k86 4K TLB linear tag:
Bit(s)	Description	(Table R0031)
 31-20	reserved (0)
 19	global valid bit
 18	TLB entry is dirty
 17	user/supervisor
 16	read/write
 15	entry is valid
 14-0	tag (bits 31-17 of address)
SeeAlso: #R0024,#R0030,#R0033

Bitfields for Am5k86 4M TLB page:
Bit(s)	Description	(Table R0032)