trmpc860.h

ppc860平台上移植uc OS的实例

/* 
 * HEADER FILE FOR Motorola MPC860 QUICC Sample Driver
 *
 * This device driver is derived from the Ethernet Bridge example from
 * Motorola.
 * It has been modified to interface to the Treck TCP/IP stack and to
 * provide readability.
 *
 * Since it is a derived work, it remains the property of Motorola Corp.
 *
 * We have left the definintions of the quicc registers as they
 * are in the QUICC user manual
 *
 * This is why they do not match TRECK coding standards.
 * Modification History
 * Date: $Date: 1998/07/08 20:32:24 $
 * Author:
 * Version:  $Revision: 1.9 $
 * Description:
 */



/*
 * Mpc860 Buffer Descriptors
 */
typedef struct tsMpc860BufDesc
{
    unsigned short bdStatus;
    unsigned short bdLength;
    void TM_FAR *  bdDataPtr;
}ttMpc860BufDesc;

typedef ttMpc860BufDesc TM_FAR * ttMpc860BufDescPtr;

/* Number of buffer descriptors */
#define TM_MPC860_ETHER_MAX_RECV_BUFD    (unsigned short)25      
#define TM_MPC860_ETHER_MAX_XMIT_BUFD    (unsigned short)50

#define TM_MPC860_SERIAL_MAX_RECV_BUFD    (unsigned short)5      
#define TM_MPC860_SERIAL_MAX_XMIT_BUFD    (unsigned short)5

/*
 * IOCTL Defines
 */
#define TM_MPC860_REFILL_SCC1   (int)0x0001
#define TM_MPC860_SEND_COMPLETE (int)0x0002


/*
 * Function Prototypes
 */

/*
 * The Actual SCC1 ISR Wrapper Function
 * it must call the tfMpc860Scc1HandlerIsr function
 * This routine may be in "C" if it is supported
 * or assembly if not.  It is VERY RTOS dependent
 * so it cannot be provided with the driver
 *
 * An example of this routine in assembly for uC/OS:

*
* The Interrupt Routine for a CPU32 to call the Mpc860 Driver
*
_tfMpc860Scc1Isr
* Save the Registers
        MOVEM.L D0-D7/A0-A6,-(A7)

* uC/OS Call to tell RTOS we are in an ISR
        JSR     _OSIntEnter

* Call the handler
        JSR     _tfMpc860Scc1HandlerIsr

* uC/OS Call to tell the RTOS that we are leaving the ISR
        JSR     _OSIntExit

* Restore the registers
        MOVEM.L (A7)+,D0-D7/A0-A6

* Return from Exception (Interrupt)
        RTE     

 */

void tfMpc860Scc1Isr(void);


int tfMpc860GetPhyAddr(ttUserInterface userInterface,
        char *address);

int tfMpc860Ioctl(ttUserInterface interfaceHandle, int flag,
                 void TM_FAR * optionPtr, int optionLen);

int tfMpc860Receive(ttUserInterface  interfaceHandle,
                   char TM_FAR    **dataPtrPtr,
                   int  TM_FAR     *lengthPtr,
                   ttUserBufferPtr  userBufferHandlePtr);

int tfMpc860Send(ttUserInterface interfaceHandle,
                char TM_FAR *buffer,
                int          len,
                int          flag);
int tfMpc860EtherOpen(ttUserInterface interfaceHandle);

int tfMpc860EtherClose(ttUserInterface interfaceHandle);

void tfMpc860Scc1HandlerIsr(void);

/*
 * Mpc860 Defines
 */
#define TM_MPC860_IMMR_LOC      0xff000000UL

/*
 * Interrupt Level for the CPIC on the 860
 */
#define TM_MPC860_CPIC_SIVEC     0x24000000			/* Level 4 */
#define TM_MPC860_CPIC_LEVEL     4UL
#define TM_MPC860_CPIC_MASK      0x00400000UL
#define TM_MPC860_CIVR_IACK      1UL

/*
 * The CICR register is used to set the vector base address, the IRQ Level
 * set the priorities of the SCC's.  If it is not set correctly then the 
 * SCC's will NEVER interrupt.
 *
 * We set it up to the following default:
 *
 * Priority: Lowest to Highest
 * SCCd = SCC4
 * SCCc = SCC3
 * SCCb = SCC2
 * SCCa = SCC1
 *
 * IRQ Level = 4
 *
 * Highest Priority = Original Order 0b11111
 *
 * Interrupt Enable = SET
 */
#define TM_MPC860_CICR_DEFAULT  0x00E40F80UL|(TM_MPC860_CPIC_LEVEL<<13)
#define TM_MPC860_BRGC_RST      0x00010000UL
#define TM_MPC860_BRGC_DIV16    0x00000001UL
/*
 * Timer Interrupt Number
 */
#define TM_MPC860_TMR1_INT      0x00000019UL

/*
 * SCC(x) Interrupt Numbers
 */
#define TM_MPC860_SCCA_INT      0x0000001eUL
#define TM_MPC860_SCCB_INT      0x0000001dUL
#define TM_MPC860_SCCC_INT      0x0000001cUL
#define TM_MPC860_SCCD_INT      0x0000001bUL

/*
 * Timer Interrupt Bit
 */
#define TM_MPC860_TMR1_INT_MASK 0x02000000UL

/* 
 * SCC(x) Interrupt Bit
 */
#define TM_MPC860_SCC1_INT_MASK 0x40000000UL
#define TM_MPC860_SCC2_INT_MASK 0x20000000UL
#define TM_MPC860_SCC3_INT_MASK 0x10000000UL
#define TM_MPC860_SCC4_INT_MASK 0x08000000UL

/* 
 * SCC(x) Commands
 */
#define TM_MPC860_INIT_RXTX_SCC1 (unsigned short)0x0001
#define TM_MPC860_INIT_RXTX_SCC2 (unsigned short)0x0041
#define TM_MPC860_INIT_RXTX_SCC3 (unsigned short)0x0081
#define TM_MPC860_INIT_RXTX_SCC4 (unsigned short)0x00C1

#define TM_MPC860_RESTART_TX (unsigned short)0x0600

/* 
 * Ethernet Defines 
 */
/* Perform 32 bit CRC */
#define TM_MPC860_ETHER_CRC_PRES         0xffffffffUL 
/* Comply with 32 bit CRC */    
#define TM_MPC860_ETHER_CRC_MASK         0xdebb20e3UL 
/* Zero for clarity */
#define TM_MPC860_ETHER_CRCEC            0x00000000UL
#define TM_MPC860_ETHER_ALEC                 0x00000000UL
#define TM_MPC860_ETHER_DISFC            0x00000000UL
#define TM_MPC860_ETHER_PADS                 0x00000000UL
/* 15 Collision Trys */
#define TM_MPC860_ETHER_RETRY_LIMIT          (unsigned short)0x000f 
/* Maxmimum Ethernet Frame Length = 1518 (DONT CHANGE) */
#define TM_MPC860_ETHER_MAX_FRAME_LEN    (unsigned short)0x05ee
/* Minimum Ethernet Frame Length = 64 (DONT CHANGE) */
#define TM_MPC860_ETHER_MIN_FRAME_LEN    (unsigned short)0x0040
/* Maximum Ethernet DMA count */
#define TM_MPC860_ETHER_MAX_DMA1_COUNT   TM_MPC860_ETHER_MAX_FRAME_LEN
#define TM_MPC860_ETHER_MAX_DMA2_COUNT   TM_MPC860_ETHER_MAX_FRAME_LEN
/* Clear the group addresses */
#define TM_MPC860_ETHER_GROUP_ADDR1          0x00000000UL
#define TM_MPC860_ETHER_GROUP_ADDR2          0x00000000UL        
#define TM_MPC860_ETHER_GROUP_ADDR3          0x00000000UL        
#define TM_MPC860_ETHER_GROUP_ADDR4          0x00000000UL        
/* Not Used */
#define TM_MPC860_ETHER_P_PER            0x00000000UL
/* Individual Hash table is not used */
#define TM_MPC860_ETHER_INDV_ADDR1           0x00000000UL
#define TM_MPC860_ETHER_INDV_ADDR2           0x00000000UL
#define TM_MPC860_ETHER_INDV_ADDR3           0x00000000UL
#define TM_MPC860_ETHER_INDV_ADDR4           0x00000000UL
/* Zeroed */
#define TM_MPC860_ETHER_T_ADDR_H         0x00000000UL 
#define TM_MPC860_ETHER_T_ADDR_M         0x00000000UL 
#define TM_MPC860_ETHER_T_ADDR_L         0x00000000UL 


/*
 * SCC Channel Numbers
 */
#define TM_MPC860_SCC1_CHANNEL 0
#define TM_MPC860_SCC2_CHANNEL 1
#define TM_MPC860_SCC3_CHANNEL 2
#define TM_MPC860_SCC4_CHANNEL 3

/*
 * SCC Parameter Ram 
 */
#define TM_MPC860_COMMAND_FLAG (unsigned short)0x0001
#define TM_MPC860_SCC1_RECV_BASE (unsigned short)0x0000  
#define TM_MPC860_SCC1_XMIT_BASE \
                TM_MPC860_SCC1_RECV_BASE + \
                (TM_MPC860_ETHER_MAX_RECV_BUFD * sizeof(struct tsMpc860BufDesc) )

#define TM_MPC860_SCC4_RECV_BASE \
                TM_MPC860_SCC1_XMIT_BASE + \
                (TM_MPC860_ETHER_MAX_XMIT_BUFD * sizeof(struct tsMpc860BufDesc) )

#define TM_MPC860_SCC4_XMIT_BASE \
                TM_MPC860_SCC4_RECV_BASE + \
                (TM_MPC860_SERIAL_MAX_RECV_BUFD * sizeof(struct tsMpc860BufDesc) )


/* Receive normal operation */ 
#define TM_MPC860_SCC1_RECV_FUNC_CODE    (unsigned short)0x18    
#define TM_MPC860_SCC4_RECV_FUNC_CODE    (unsigned short)0x15    
/* Transmit normal operation */ 
#define TM_MPC860_SCC1_XMIT_FUNC_CODE    (unsigned short)0x18 
#define TM_MPC860_SCC4_XMIT_FUNC_CODE    (unsigned short)0x15 
/* Max ethernet frame length (Divisable by 4)*/ 
#define TM_MPC860_SCC1_MAX_RECV_BUF_LEN  (unsigned short)1520

#define TM_MPC860_SCC4_MAX_RECV_BUF_LEN  (unsigned short)2048
#define TM_MPC860_SCC4_MAX_IDL16         (unsigned short)0x10        

#define TM_MPC860_SCC_FRAME_SYNC_ETHER   (unsigned short)0xd555


/*
 * Port A Registers
 */
#define TM_MPC860_PORTA_PA0  (unsigned short)0x8000
#define TM_MPC860_PORTA_PA1  (unsigned short)0x4000
#define TM_MPC860_PORTA_PA2  (unsigned short)0x2000
#define TM_MPC860_PORTA_PA3  (unsigned short)0x1000
#define TM_MPC860_PORTA_PA4  (unsigned short)0x0800
#define TM_MPC860_PORTA_PA5  (unsigned short)0x0400
#define TM_MPC860_PORTA_PA6  (unsigned short)0x0200
#define TM_MPC860_PORTA_PA7  (unsigned short)0x0100
#define TM_MPC860_PORTA_PA8  (unsigned short)0x0080
#define TM_MPC860_PORTA_PA9  (unsigned short)0x0040
#define TM_MPC860_PORTA_PA10 (unsigned short)0x0020
#define TM_MPC860_PORTA_PA11 (unsigned short)0x0010
#define TM_MPC860_PORTA_PA12 (unsigned short)0x0008
#define TM_MPC860_PORTA_PA13 (unsigned short)0x0004
#define TM_MPC860_PORTA_PA14 (unsigned short)0x0002
#define TM_MPC860_PORTA_PA15 (unsigned short)0x0001

/*
 * Port B Registers
 */
#define TM_MPC860_PORTB_PB0  0x80000000UL
#define TM_MPC860_PORTB_PB1  0x40000000UL
#define TM_MPC860_PORTB_PB2  0x20000000UL
#define TM_MPC860_PORTB_PB3  0x10000000UL
#define TM_MPC860_PORTB_PB4  0x08000000UL
#define TM_MPC860_PORTB_PB5  0x04000000UL
#define TM_MPC860_PORTB_PB6  0x02000000UL
#define TM_MPC860_PORTB_PB7  0x01000000UL
#define TM_MPC860_PORTB_PB8  0x00800000UL
#define TM_MPC860_PORTB_PB9  0x00400000UL
#define TM_MPC860_PORTB_PB10 0x00200000UL
#define TM_MPC860_PORTB_PB11 0x00100000UL
#define TM_MPC860_PORTB_PB12 0x00080000UL
#define TM_MPC860_PORTB_PB13 0x00040000UL
#define TM_MPC860_PORTB_PB14 0x00020000UL
#define TM_MPC860_PORTB_PB15 0x00010000UL
#define TM_MPC860_PORTB_PB16 0x00008000UL
#define TM_MPC860_PORTB_PB17 0x00004000UL
#define TM_MPC860_PORTB_PB18 0x00002000UL
#define TM_MPC860_PORTB_PB19 0x00001000UL
#define TM_MPC860_PORTB_PB20 0x00000800UL
#define TM_MPC860_PORTB_PB21 0x00000400UL
#define TM_MPC860_PORTB_PB22 0x00000200UL