📄 crt0.s
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mtspr 22,r3
isync
#------------------------------------------------------------------------
# Initialize Core registers
#------------------------------------------------------------------------
lis r3,0x0000 # MSR and SRR1 = 0x00001002
ori r3,r3,0x9002
mtmsr r3
mtspr SRR1,r3
lis r3,0x0 # DER = 0
ori r3,r3,0x0
mtspr DER,r3
lis r3,0x0000 # ICTRL = 6
ori r3,r3,0x0006
mtspr ICTRL,r3
lis r3,0x0000 # ICR = 0
ori r3,r3,0x0000
mtspr ICR,r3
.if TM_SPEED40=1
# Set CPU Clock to 40MHZ from 5MHZ osc
lis r3,0x0070
stw r3,PLPRCR(r4)
.elsec #/* speed not defined assume 25 */
# Set CPU Clock to 25MHZ from 5MHZ osc
lis r3,0x0040
stw r3,PLPRCR(r4)
.endc
#------------------------------------------------------------------------
# Initialize SIU registers
#------------------------------------------------------------------------
lwz r3,SIUMCR(r4) # SIUMCR = The old value bitwize
oris r3,r3,0x0060 # ored with 0x00600040
ori r3,r3,0x0040
stw r3,SIUMCR(r4)
#
# Watch Dog Timer
#
lis r3,0xffff # SYPCR = 0xffffff08
ori r3,r3,0xff08
stw r3,SYPCR(r4)
li r3,0x556c
sth r3,SWSR(r4)
li r3,0xAA93
sth r3,SWSR(r4)
# Setup Chip Selects
# CS0 = Boot ROM
SetCSReg RomBase+0x0401,BR0
SetCSReg 0xFFF80D30,OR0
UPMInit:
LA r5,UpmTable
LA r6,UpmTableEnd
sub r7,r6,r5 # UpmTableEnd - UpmTable
srawi r7,r7,2 # /4
li r6,0x0000 # Command: OP=Write, UPMA, MAD=0
UpmWriteLoop:
lwz r3,0(r5) # get data from table
stw r3,MDR(r4) # store the data to MD register
stw r6,MCR(r4) # issue command to MCR register
addi r5,r5,4 # next entry in the table
addi r6,r6,1 # next MAD address
cmp r6,r7 # done yet ?
blt UpmWriteLoop
# CS1 = DRAM Bank 1
SetCSReg 0xFFC00800,OR1
SetCSReg RamBase+0x0081,BR1
# set up refresh for 15.6
# uses MPTPR & MSB of MAMR
li r8,0x0200 # Memory Periodic Timer Clk = CPU CLK/32
sth r8,MPTPR(r4)
.if TM_SPEED40=1
lis r8,0x1480 ; set PTA,PTAE
ori r8,r8,0x00001334 ; set DSA,G0CLA,RFLA,WLFA,TLFA
.elsec
lis r8,0x0C80 ; set PTA,PTAE
ori r8,r8,0x00001334 ; set DSA,G0CLA,RFLA,WLFA,TLFA
.endc
;*** Initially set for 4 MB
LA r5,0xFF8FFFFF
and r8,r8,r5 ; clear AMA
LA r5,0x00200000
or r8,r8,r5 ; Set AMA
stw r8,MAMR(r4) ; set MAMR
SetCSReg 0xFFC00800,OR1
SetCSReg RamBase+0x0081,BR1
;*** Wait at least 200 usec for DRAM to stabilize
lis r5,0x0000 # count 0x0379 times ~225nsec
ori r5,r5,0x379
lis r6,0x0000 # clear r6
delayloop4:
addi r6,r6,0x01 # decrement the counter
cmpw cr0,r6,r5 # done yet ?
bne delayloop4
;*** Need at least 10 DRAM accesses to stabilize
lis r5,0x0000 # count 10 times
ori r5,r5,0x0a
lis r6,0x0000 # clear r6
lis r15,RamBase # load address
ori r15,r15,0x1000
lis r16,0x1234 # load data
ori r16,r16,0x5678
ramloop:
stw r16,0(r15)
lwz r16,0(r15)
addi r6,r6,0x01 # decrement the counter
cmpw cr0,r6,r5 # done yet ?
bne ramloop
# CS4 = Network Interface Modules
SetCSReg 0xFFFF0182,OR4
SetCSReg 0x40000401,BR4
# CS5 = DRAM ID Register
SetCSReg 0xFFFF0122,OR5
SetCSReg 0x50000401,BR5
mfspr r8,DC_CST
#
#************************************************************************
# Cache Initialization
#
# Function: CacheInit
# If the Data cache is enabled, flush then
# disable it so we can finish the rest of initialization
#
# Input Registers:
# R8 contains the content of DC_CST before enterring
# usr_init()
#
# Output Registers:
# R3, R7, R5 and R6 will be destroyed
#************************************************************************
#
CacheInit:
#------------------------------------------------------------------------
# If Instruction cache was enabled, disable and invalidate all
#------------------------------------------------------------------------
ICacheInit:
mfspr r3,IC_CST # read I-cache CSR
andis. r3,r3,CacheEnableBit
beq ICacheUnlock # no, Icache was disabled
lis r3,CacheDisableCmd
mtspr IC_CST,r3 # disable Icache
isync
ICacheUnlock:
lis r3,CacheUnlockAllCmd
mtspr IC_CST,r3 # Unlock Icache
isync
ICacheInv:
lis r3,CacheInvAllCmd
mtspr IC_CST,r3 # Invalidate Icache
isync
ICacheEnable:
lis r3,CacheEnableCmd
mtspr IC_CST,r3 # Enable Icache
isync
DCacheInit:
DCacheUnlock:
lis r3,CacheUnlockAllCmd
sync
mtspr DC_CST,r3 # Unlock Dcache
andis. r8,r8,CacheEnableBit # Was DCache enabled ?
beq DCacheInv # no, Dcache was disabled
DCacheFlushAll:
li r3,0 # Read 1 word per cache line
li r6,0 # Read 1 word per cache line
# for 800 lines
li r7,256 # 2 ways, 128 sets per way
DCacheFlushLoop:
addic. r7,r7,-1 # decrementer, set cc bit
lwz r5,0(r3) # access memory
dcbf r6,r3 # flush the line
addi r3,r3,16 # next line
bgt DCacheFlushLoop
DCacheDisable:
lis r3,CacheDisableCmd
sync
mtspr DC_CST,r3 # disable Dcache
DCacheInv:
lis r3,CacheInvAllCmd
sync
mtspr DC_CST,r3 # Invalidate Dcache
DCacheEnable:
lis r3,CacheEnableCmd
sync
# mtspr DC_CST,r3 # Enable Icache
# Return from __tfInit860
blr
.if TM_SPEED40=1 #/* assumes 60 NS drams */
# /* UPMA contents: */
UpmTable:
# /* single read. (offset 0 in upm RAM) */
.long 0x0fffcc24, 0x0fffcc04, 0x00ffcc00, 0x71ffcc07
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
# /* burst read. (offset 8 in upm RAM) */
.long 0x0fffcc24, 0x0fffcc04, 0x00ffcc80, 0x03ffcccc
.long 0x00ffcc00, 0x73ffcc07, 0xffffcc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffe04, 0xfffffc04, 0xfffffc04, 0xfffffc04
# /* single write. (offset 18 in upm RAM) */
.long 0x0fafec24, 0x0fafec04, 0x00afec00, 0x73bfec07
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
# /* burst write. (offset 20 in upm RAM) */
.long 0x0fafec24, 0x0fafec04, 0x00afec80, 0x0fafeccc
.long 0x00afec00, 0x7fbfec07, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
# /* refresh. (offset 30 in upm RAM) */
.long 0xf0ffec04, 0x00ffec04, 0x01ffec04, 0x3fffec04
.long 0xffffec04, 0xffffec05, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
# /* exception. (offset 3c in upm RAM) */
.long 0xffffec07, 0xfffffc04, 0xfffffc04, 0xfffffc04
#
UpmTableEnd:
.elsec # speed not defined
UpmTable:
# UPM contents for the default 860 memory configuration:
.if TM_DRAM60NS
# /* DRAM 60ns - single read. (offset 0 in upm RAM) */
# /* offsets 6-7 not used */
.long 0x0FFFCC04, 0x00FFCC00, 0xF1FFCC05, 0xFFFFFC04
.long 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
# /* DRAM 60ns - burst read. (offset 8 in upm RAM) */
# /* offsets 16-17 not used */
.long 0x0FFFEC04, 0x00FFEC08, 0x04FFEC40, 0x02FFCC4C
.long 0x00FFEC08, 0x04FFEC40, 0x33FFCC07, 0xFFFFFC04
.long 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
.long 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
# /* DRAM 60ns - single write. (offset 18 in upm RAM) */
# /* offsets 1d-1f not used */
.long 0x0FAFEC00,0x11BFEC07, 0xFFFFFC04, 0xFFFFFC04
.long 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
# /* DRAM 60ns - burst write. (offset 20 in upm RAM) */
# /* offsets 2a-2f not used */
.long 0x0FAFEC00, 0x01AFEC4C, 0x08AFEC00, 0x01AFEC4C
.long 0x08AFEC00, 0x01AFEC4C, 0x08AFEC00, 0x11BFEC07
.long 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
.long 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
# /* refresh 60ns. (offset 30 in upm RAM) */
# /* offsets 37-3b not used */
.long 0xC0FFEC04, 0x03FFEC04, 0x3FFFEC04, 0xFFFFEC05
.long 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
.long 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
# /* exception. (offset 3c in upm RAM) */
# /* offset 3d-3f not used */
#
.long 0xFFFFEC07, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04
.endc
.if TM_DRAM70NS
# /* DRAM 70ns - single read. (offset 0 in upm RAM) */
# /* offsets 6-7 not used */
.long 0x0fffcc24, 0x0fffcc04, 0x0cffcc04
.long 0x00ffcc04, 0x00ffcc00, 0x37ffcc47
.long 0xffffffff, 0xffffffff
# /* DRAM 70ns - burst read. (offset 8 in upm RAM) */
# /* offsets 16-17 not used */
.long 0x0fffcc24, 0x0fffcc04, 0x08ffcc04, 0x00ffcc04
.long 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00
.long 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04
.long 0x00ffec00, 0x3fffec47
.long 0xffffffff, 0xffffffff
# /* DRAM 70ns - single write. (offset 18 in upm RAM) */
# /* offsets 1d-1f not used */
.long 0x0fafcc24, 0x0fafcc04, 0x08afcc04, 0x00afcc00, 0x37ffcc47
.long 0xffffffff, 0xffffffff, 0xffffffff
# /* DRAM 70ns - burst write. (offset 20 in upm RAM) */
# /* offsets 2a-2f not used */
.long 0x0fafcc24, 0x0fafcc04, 0x08afcc00, 0x07afcc4c
.long 0x08afcc00, 0x07afcc4c, 0x08afcc00, 0x07afcc4c
.long 0x08afcc00, 0x37afcc47
.long 0xffffffff, 0xffffffff, 0xffffffff
.long 0xffffffff, 0xffffffff, 0xffffffff
# /* refresh 70ns. (offset 30 in upm RAM) */
# /* offsets 37-3b not used */
# /* exception. (offset 3c in upm RAM) */
# /* offset 3d-3f not used */
#
.long 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04
.long 0x7fffcc04, 0xffffcc86, 0xffffcc05
.long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
.long 0x33ffcc07
.long 0xffffffff, 0xffffffff, 0x40004650
.endc
UpmTableEnd:
.endc #/* no speed defined */
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