osdefs.h

各种硬件平台上的us OS移植实例(arm6)

/*> osdefs.h <*/
/*---------------------------------------------------------------------------*/
/* $Revision: 0.1 $
 *   $Author: jsmith $
 *     $Date: 941103 $
 *
 * uC/OS Real-time multitasking kernel for the ARM processor.
 * Copyright (C) 1992 Jean J. Labrosse.
 * Copyright (c) 1994, VLSI Technology Inc. All Rights Reserved.
 *
 * VLSI Technology Inc. does not assume any liability arising out of
 * this program or use thereof.
 */
/*---------------------------------------------------------------------------*/

#ifndef __ucos_osdefs_h
#define __ucos_osdefs_h

/*---------------------------------------------------------------------------*/

#include "swi.h"    /* C-Demon SWI interface */
#include "driver.h" /* target architecture description */

/*---------------------------------------------------------------------------*/
/* The following typedefs are used to describe the prototypes for
 * individual source bit IRQ and FIQ handlers within uC/OS. The
 * routines are called from within the relevant interrupt mode, with
 * the relevant interrupt disabled. There is a limited number of uC/OS
 * calls that the routines can safely make (documented in the
 * kern600.s source).
 */
typedef void (*IRQHandlerFn)(void) ;
typedef void (*FIQHandlerFn)(void) ;

/* These routines are the default handlers placed into the respective
 * interrupt handler vectors:
 */
extern IRQHandlerFn DummyIRQ ;
extern FIQHandlerFn DummyFIQ ;

extern IRQHandlerFn ARMInstallIRQHandler(int slot,IRQHandlerFn newfn) ;
extern FIQHandlerFn ARMInstallFIQHandler(int slot,FIQHandlerFn newfn) ;

/* The following prototypes are present to allow the hi-level
 * initialisation code to reference the lo-level uC/OS ARM vector
 * handlers. The routines are *NOT* APCS-3 conforming, so should
 * never actually be called directly.
 */
extern void IRQHandler(void) ;
extern void FIQHandler(void) ;

/*---------------------------------------------------------------------------*/

/* idle task stack size (words) */
#define OS_IDLE_STK_SIZE        32      
 
/*
 * Global variables.
 */
extern  uint    OSCtxSwCtr;             /* context switches counter */
extern  uint    OSIdleCtr;              /* idle counter */
extern  uint    OSRunning;              /* kernel running flag */
extern  OS_TCB  *OSTCBCur;              /* current running TCB pointer */
extern  OS_TCB  *OSTCBHighRdy;          /* highest priority TCB ready to run */
extern  OS_TCB  *OSTCBPrioTbl[];        /* table of pointers to created TCBs */
 
/* constants */
#define	SVC32MODE		0x13			/* VLSI */
#define TimerIRQNum		1				/* VLSI */
#define	INT_MAX			0x7FFFFFF0		/* VLSI */

/* task status */
#define	OS_STAT_RDY		0	/* ready to run */
#define	OS_STAT_SEM		1	/* suspended on semaphore */
#define	OS_STAT_MBOX	2	/* suspended on mailbox */
#define	OS_STAT_Q		3	/* suspended on queue */

/*---------------------------------------------------------------------------*/
/* We provide in-line macros to perform the interrupt enable and
 * disable. These will execute slightly quicker than a call to an
 * APCS-3 conforming function, and will affect the code generator
 * less.
 *
 * The macros will simply update the CPSR if the thread is currently
 * executing in a priviledged ARM mode. However USR threads need to
 * perform a SWI to enter SVC mode to allow the IRQ and FIQ flags to
 * be updated.
 *
 * We use "_word" to introduce fixed instructions, since the compiler
 * only has global register allocations and not local ones. If we used
 * a global register allocation (__global_reg(n)) then that register
 * would be lost to the rest of the world.
 *
 * If code size becomes an issue then these in-line versions could be
 * placed into small functions.
 */

/* NASTY ARM constants, but this is the easiest way */
#define ARM_STMFD_sp_a1_a2  	(0xE92D0003) /* STMFD sp!,{a1,a2} */
#define ARM_MRS_a1_cpsr     	(0xE10F0000) /* MRS   a1,CPSR */
#define ARM_BIC_a1_INT	    	(0xE3C000C0) /* BIC   a1,a1,#NoInt */
#define ARM_ORR_a1_INT	    	(0xE38000C0) /* ORR   a1,a1,#NoInt */
#define ARM_TST_a1_SubModeMask	(0xE310000F) /* TST   a1,#SubModeMask */
#define ARM_SWIEQ(swinum)   	(0x0F000000 | ((swinum & 0x00FFFFFF)))
#define ARM_MSR_CPSR_a1	    	(0xE129F000) /* MSR   CPSR,a1 */
#define ARM_LDMFD_sp_a1_a2  	(0xE8BD0003) /* LDMFD sp!,{a1,a2} */

#define OS_ENTER_CRITICAL() {	    	    	    	    	\
    	    	    	     _word(ARM_STMFD_sp_a1_a2) ;    	\
    	    	    	     _word(ARM_MRS_a1_cpsr) ;	    	\
    	    	    	     _word(ARM_ORR_a1_INT) ;	    	\
    	    	    	     _word(ARM_TST_a1_SubModeMask) ;	\
    	    	    	     _word(ARM_SWIEQ(SWIEnterOS)) ; 	\
    	    	    	     _word(ARM_MSR_CPSR_a1) ;	    	\
    	    	    	     _word(ARM_LDMFD_sp_a1_a2) ;    	\
    	    	    	    }

#define OS_EXIT_CRITICAL() {	    	    	    	    	\
    	    	    	    _word(ARM_STMFD_sp_a1_a2) ;    	\
    	    	    	    _word(ARM_MRS_a1_cpsr) ;	    	\
    	    	    	    _word(ARM_BIC_a1_INT) ;	    	\
    	    	    	    _word(ARM_TST_a1_SubModeMask) ;	\
    	    	    	    _word(ARM_SWIEQ(SWIEnterOS)) ; 	\
    	    	    	    _word(ARM_MSR_CPSR_a1) ;	    	\
    	    	    	    _word(ARM_LDMFD_sp_a1_a2) ;    	\
    	    	    	   }

/*---------------------------------------------------------------------------*/

#endif /* __ucos_osdefs_h */

/*---------------------------------------------------------------------------*/
/*> EOF osdefs.h <*/