zz80.c

DGen源码最后版本

			case 0xDB: // in_a_byte 
			{
				BYTE bPort = ImmedByte();
				cCycles -= 11;
				m_regA = InRaw ( bPort );
				break;
			}
			
			case 0xDC: // call_c
				cCycles -= 10;
				cCycles -= Call0(m_regF & C_FLAG);
				break;
			
			case 0xDD: // dd
				cCycles -= HandleDD();
				break;
			
			case 0xDE: // sbc_a_byte
				cCycles -= 7;
				Sbc_1(ImmedByte());
				break;
			
			case 0xDF: // rst_18
				cCycles -= 11;
				Rst(0x18);
				break;

			case 0xE0: // ret_po
				cCycles -= 5;
				cCycles -= Ret1(m_regF & V_FLAG);
				break;
			
			case 0xE1: // pop_hl
				cCycles -= 10;
				m_regHL = Pop();
				break;
			
			case 0xE2: // jp_po
				cCycles -= 10;
				cCycles -= Jp1(m_regF & V_FLAG);
				break;
			
			case 0xE3: // ex_xsp_hl
				cCycles -= 19;
			{
				int i = MemReadWord(GetSP());
				MemWriteWord(GetSP(), m_regHL);
				m_regHL = i;
				break;
			}
			
			case 0xE4: // call_po
				cCycles -= 10;
				cCycles -= Call1(m_regF & V_FLAG);
				break;
			
			case 0xE5: // push_hl
				cCycles -= 11;
				Push(m_regHL);
				break;
			
			case 0xE6: // and_byte
				cCycles -= 7;
				And(ImmedByte());
				break;
			
			case 0xE7: // rst_20
				cCycles -= 11;
				Rst(0x20);
				break;

			case 0xE8: // ret_pe
				cCycles -= 5;
				cCycles -= Ret0(m_regF & V_FLAG);
				break;
			
			case 0xE9: // jp_hl
				cCycles -= 4;
				SetPC(m_regHL);
				break;
			
			case 0xEA: // jp_pe
				cCycles -= 10;
				cCycles -= Jp0(m_regF & V_FLAG);
				break;
			
			case 0xEB: // ex_de_hl
				cCycles -= 4;
				swap(m_regDE, m_regHL);
				break;
			
			case 0xEC: // call_pe
				cCycles -= 10;
				cCycles -= Call0(m_regF & V_FLAG);
				break;
			
			case 0xED: // ed
				cCycles -= HandleED(cCycles);
				break;
			
			case 0xEE: // xor_byte
				cCycles -= 7;
				Xor(ImmedByte());
				break;
			
			case 0xEF: // rst_28
				cCycles -= 11;
				Rst(0x28);
				break;

			case 0xF0: // ret_p
				cCycles -= 5;
				cCycles -= Ret1(m_regF & S_FLAG);
				break;
			
			case 0xF1: // pop_af
				cCycles -= 10;
				m_regAF = Pop();
				break;
			
			case 0xF2: // jp_p
				cCycles -= 10;
				cCycles -= Jp1(m_regF & S_FLAG);
				break;
			
			case 0xF3: // di
				cCycles -= 4;
				Di();
				break;
			
			case 0xF4: // call_p
				cCycles -= 10;
				cCycles -= Call1(m_regF & S_FLAG);
				break;
			
			case 0xF5: // push_af
				cCycles -= 11;
				Push(m_regAF);
				break;
			
			case 0xF6: // or_byte
				cCycles -= 7;
				Or(ImmedByte());
				break;
			
			case 0xF7: // rst_30
				cCycles -= 11;
				Rst(0x30);
				break;

			case 0xF8: // ret_m   
				cCycles -= 5;
				cCycles -= Ret0(m_regF & S_FLAG);
				break;
			
			case 0xF9: // ld_sp_hl
				cCycles -= 6;
				SetSP(m_regHL);
				break;
			
			case 0xFA: // jp_m
				cCycles -= 10;
				cCycles -= Jp0(m_regF & S_FLAG);
				break;
			
			case 0xFB: // ei
				cCycles -= 4;
				cCycles -= Ei();
//				if (m_fPendingInterrupt)
				{
//					return (cCyclesArg - cCycles);
				}
				break;
			
			case 0xFC: // call_m
				cCycles -= 10;
				cCycles -= Call0(m_regF & S_FLAG);
				break;
			
			case 0xFD: // fd
				cCycles -= HandleFD();
				break;
			
			case 0xFE: // cp_byte    
				cCycles -= 7;
				Cp(ImmedByte());
				break;
			
			case 0xFF: // rst_38
				cCycles -= 11;
				Rst(0x38);
				break;

			default:
				assert(FALSE);
				break;
		}
	}

z80ExecBottom:
	z80pc = GetPC(); /* for some of the platforms */
	dwElapsedTicks = origElapsedTicks + (cCyclesArg - cCycles);
	return ( 0x80000000 );
}

UINT32 mz80int ( UINT32 bVal ) {
	if (m_iff1 == 0) // is IRQ disabled?
		return 0xffffffff;		// Interrupt not taken!
		
	m_fPendingInterrupt = FALSE;

	m_iff1 = 0;

	if (m_fHalt)
	{
		SetPC(GetPC() + 1);
		m_fHalt = FALSE;
	}

	if (0 == m_nIM || 1 == m_nIM)
	{
		Rst(z80intAddr);
		return(0);		// We took the interrupt
	}

	Push(GetPC());
	SetPC(MemReadWord(MAKEWORD(bVal, m_regI)));

	return(0); // fix-me
}

UINT32 mz80nmi ( void ) {
	m_iff1 = 0;

	if (m_fHalt)
	{
		SetPC(GetPC() + 1);
		m_fHalt = FALSE;
	}
	
	Rst(z80nmiAddr);

	return(0);
}

/* ***************************************************************************
 * Flow of Control
 * ***************************************************************************
 */

/* inline */ int Jr0(int f) {
	if (f)
	{
		AdjustPC((signed char)ImmedByte());
		return 5;
	}
	else
	{
		AdjustPC(1);
		return 0;
	}
}

/* inline */ int Jr1(int f) {
	if (f)
	{
		AdjustPC(1);
		return 0;
	}
	else
	{
		AdjustPC((signed char)ImmedByte());
		return 5;
	}
}

/* inline */ int Call0(int f) {
	char string[150];

	if (f)
	{
		WORD wAddr = ImmedWord();
		Push(GetPC());
		SetPC(wAddr);
		return 7;
	}
	else
	{
		AdjustPC(2);
		return 0;
	}
}

/* inline */ int Call1(int f) {
	if (f)
	{
		AdjustPC(2);
		return 0;
	}
	else
	{
		WORD wAddr = ImmedWord();
		Push(GetPC());
		SetPC(wAddr);
		return 7;
	}
}

/* inline */ int Jp0(int f) {
	if (f)
	{
		SetPC(ImmedWord());
		return 0; // ????????????????
	}
	else
	{
		AdjustPC(2);
		return 0;
	}
}

/* inline */ int Jp1(int f) {
	if (f)
	{
		AdjustPC(2);
		return 0;
	}
	else
	{
		SetPC(ImmedWord());
		return 0; // ????????????????
	}
}

/* inline */ void Rst(WORD wAddr) {
	Push(GetPC());
	SetPC(wAddr);
}

/* ***************************************************************************
 * CB prefixed instructions
 * ***************************************************************************
 */

int HandleCB() {
	const BYTE bOpcode = ImmedByte();
	m_regR++;

	switch (bOpcode)
	{
		case 0x00: // rlc_b
			m_regB = Rlc(m_regB);
			return 8;
		
		case 0x01: // rlc_c  
			m_regC = Rlc(m_regC);
			return 8;
		
		case 0x02: // rlc_d  
			m_regD = Rlc(m_regD);
			return 8;
		
		case 0x03: // rlc_e  
			m_regE = Rlc(m_regE);
			return 8;
		
		case 0x04: // rlc_h  
			m_regH = Rlc(m_regH);
			return 8;
		
		case 0x05: // rlc_l  
			m_regL = Rlc(m_regL);
			return 8;
		
		case 0x06: // rlc_xhl  
			MemWriteByte(m_regHL, Rlc(MemReadByte(m_regHL)));
			return 15;
		
		case 0x07: // rlc_a  
			m_regA = Rlc(m_regA);
			return 8;

		case 0x08: // rrc_b  
			m_regB = Rrc(m_regB);
			return 8;
		
		case 0x09: // rrc_c  
			m_regC = Rrc(m_regC);
			return 8;
		
		case 0x0A: // rrc_d  
			m_regD = Rrc(m_regD);
			return 8;
		
		case 0x0B: // rrc_e  
			m_regE = Rrc(m_regE);
			return 8;
		
		case 0x0C: // rrc_h  
			m_regH = Rrc(m_regH);
			return 8;
		
		case 0x0D: // rrc_l  
			m_regL = Rrc(m_regL);
			return 8;
		
		case 0x0E: // rrc_xhl  
			MemWriteByte(m_regHL, Rrc(MemReadByte(m_regHL)));
			return 15;
		
		case 0x0F: // rrc_a  
			m_regA = Rrc(m_regA);
			return 8;

		case 0x10: // rl_b   
			m_regB = Rl(m_regB);
			return 8;
		
		case 0x11: // rl_c   
			m_regC = Rl(m_regC);
			return 8;
		
		case 0x12: // rl_d   
			m_regD = Rl(m_regD);
			return 8;
		
		case 0x13: // rl_e   
			m_regE = Rl(m_regE);
			return 8;
		
		case 0x14: // rl_h   
			m_regH = Rl(m_regH);
			return 8;
		
		case 0x15: // rl_l   
			m_regL = Rl(m_regL);
			return 8;
		
		case 0x16: // rl_xhl   
			MemWriteByte(m_regHL, Rl(MemReadByte(m_regHL)));
			return 15;
		
		case 0x17: // rl_a   
			m_regA = Rl(m_regA);
			return 8;

		case 0x18: // rr_b   
			m_regB = Rr(m_regB);
			return 8;
		
		case 0x19: // rr_c   
			m_regC = Rr(m_regC);
			return 8;
		
		case 0x1A: // rr_d   
			m_regD = Rr(m_regD);
			return 8;
		
		case 0x1B: // rr_e   
			m_regE = Rr(m_regE);
			return 8;
		
		case 0x1C: // rr_h   
			m_regH = Rr(m_regH);
			return 8;
		
		case 0x1D: // rr_l   
			m_regL = Rr(m_regL);
			return 8;
		
		case 0x1E: // rr_xhl   
			MemWriteByte(m_regHL, Rr(MemReadByte(m_regHL)));
			return 15;
		
		case 0x1F: // rr_a   
			m_regA = Rr(m_regA);
			return 8;

		case 0x20: // sla_b  
			m_regB = Sla(m_regB);
			return 8;
		
		case 0x21: // sla_c  
			m_regC = Sla(m_regC);
			return 8;
		
		case 0x22: // sla_d  
			m_regD = Sla(m_regD);
			return 8;
		
		case 0x23: // sla_e  
			m_regE = Sla(m_regE);
			return 8;
		
		case 0x24: // sla_h  
			m_regH = Sla(m_regH);
			return 8;
		
		case 0x25: // sla_l  
			m_regL = Sla(m_regL);
			return 8;
		
		case 0x26: // sla_xhl  
			MemWriteByte(m_regHL, Sla(MemReadByte(m_regHL)));
			return 15;
		
		case 0x27: // sla_a  
			m_regA = Sla(m_regA);
			return 8;

		case 0x28: // sra_b  
			m_regB = Sra(m_regB);
			return 8;
		
		case 0x29: // sra_c  
			m_regC = Sra(m_regC);
			return 8;
		
		case 0x2A: // sra_d  
			m_regD = Sra(m_regD);
			return 8;
		
		case 0x2B: // sra_e  
			m_regE = Sra(m_regE);
			return 8;
		
		case 0x2C: // sra_h  
			m_regH = Sra(m_regH);
			return 8;
		
		case 0x2D: // sra_l  
			m_regL = Sra(m_regL);
			return 8;
		
		case 0x2E: // sra_xhl  
			MemWriteByte(m_regHL, Sra(MemReadByte(m_regHL)));
			return 15;
		
		case 0x2F: // sra_a  
			m_regA = Sra(m_regA);
			return 8;

		case 0x30: // sll_b  
			m_regB = Sll(m_regB);
			return 8;
		
		case 0x31: // sll_c  
			m_regC = Sll(m_regC);
			return 8;
		
		case 0x32: // sll_d  
			m_regD = Sll(m_regD);
			return 8;
		
		case 0x33: // sll_e  
			m_regE = Sll(m_regE);
			return 8;
		
		case 0x34: // sll_h  
			m_regH = Sll(m_regH);
			return 8;
		
		case 0x35: // sll_l  
			m_regL = Sll(m_regL);
			return 8;
		
		case 0x36: // sll_xhl  
			MemWriteByte(m_regHL, Sll(MemReadByte(m_regHL)));
			return 15;
		
		case 0x37: // sll_a  
			m_regA = Sll(m_regA);
			return 8;

		case 0x38: // srl_b  
			m_regB = Srl(m_regB);
			return 8;
		
		case 0x39: // srl_c  
			m_regC = Srl(m_regC);
			return 8;
		
		case 0x3A: // srl_d  
			m_regD = Srl(m_regD);
			return 8;
		
		case 0x3B: // srl_e  
			m_regE = Srl(m_regE);
			return 8;
		
		case 0x3C: // srl_h  
			m_regH = Srl(m_regH);
			return 8;
		
		case 0x3D: // srl_l  
			m_regL = Srl(m_regL);
			return 8;
		
		case 0x3E: // srl_xhl  
			MemWriteByte(m_regHL, Srl(MemReadByte(m_regHL)));
			return 15;
		
		case 0x3F: // srl_a  
			m_regA = Srl(m_regA);
			return 8;

		case 0x40: // bit_0_b
			Bit(m_regB, 0);
			return 8;
		
		case 0x41: // bit_0_c
			Bit(m_regC, 0);
			return 8;
		
		case 0x42: // bit_0_d
			Bit(m_regD, 0);
			return 8;
		
		case 0x43: // bit_0_e
			Bit(m_regE, 0);
			return 8;
		
		case 0x44: // bit_0_h
			Bit(m_regH, 0);
			return 8;
		
		case 0x45: // bit_0_l
			Bit(m_regL, 0);
			return 8;
		
		case 0x46: // bit_0_xhl
			Bit(MemReadByte(m_regHL), 0);
			return 12;
		
		case 0x47: // bit_0_a
			Bit(m_regA, 0);
			return 8;

		case 0x48: // bit_1_b
			Bit(m_regB, 1);
			return 8;
		
		case 0x49: // bit_1_c
			Bit(m_regC, 1);
			return 8;
		
		case 0x4A: // bit_1_d
			Bit(m_regD, 1);
			return 8;
		
		case 0x4B: // bit_1_e
			Bit(m_regE, 1);
			return 8;
		
		case 0x4C: // bit_1_h
			Bit(m_regH, 1);
			return 8;
		
		case 0x4D: // bit_1_l
			Bit(m_regL, 1);
			return 8;
		
		case 0x4E: // bit_1_xhl
			Bit(MemReadByte(m_regHL), 1);
			return 12;
		
		case 0x4F: // bit_1_a
			Bit(m_regA, 1);
			return 8;

		case 0x50: // bit_2_b
			Bit(m_regB, 2);
			return 8;
		
		case 0x51: // bit_2_c
			Bit(m_regC, 2);
			return 8;
		
		case 0x52: // bit_2_d
			Bit(m_regD, 2);
			return 8;
		
		case 0x53: // bit_2_e
			Bit(m_regE, 2);
			return 8;
		
		case 0x54: // bit_2_h
			Bit(m_regH, 2);
			return 8;
		
		case 0x55: // bit_2_l
			Bit(m_regL, 2);
			return 8;
		
		case 0x56: // bit_2_xhl
			Bit(MemReadByte(m_regHL), 2);
			return 12;
		
		case 0x57: // bit_2_a
			Bit(m_regA, 2);
			return 8;

		case 0x58: // bit_3_b
			Bit(m_regB, 3);
			return 8;
		
		case 0x59: // bit_3_c
			Bit(m_regC, 3);
			return 8;
		
		case 0x5A: // bit_3_d
			Bit(m_regD, 3);
			return 8;
		
		case 0x5B: // bit_3_e
			Bit(m_regE, 3);
			return 8;
		
		case 0x5C: // bit_3_h