zz80.c

DGen源码最后版本

				break;
			
			case 0x53: // ld_d_e    
				cCycles -= 4;
				m_regD = m_regE;
				break;
			
			case 0x54: // ld_d_h  
				cCycles -= 4;
				m_regD = m_regH;
				break;
			
			case 0x55: // ld_d_l  
				cCycles -= 4;
				m_regD = m_regL;
				break;
			
			case 0x56: // ld_d_xhl   
				cCycles -= 7;
				m_regD = MemReadByte(m_regHL);
				break;
			
			case 0x57: // ld_d_a  
				cCycles -= 4;
				m_regD = m_regA;
				break;

			case 0x58: // ld_e_b  
				cCycles -= 4;
				m_regE = m_regB;
				break;
			
			case 0x59: // ld_e_c    
				cCycles -= 4;
				m_regE = m_regC;
				break;
			
			case 0x5A: // ld_e_d     
				cCycles -= 4;
				m_regE = m_regD;
				break;
			
			case 0x5B: // ld_e_e    
				cCycles -= 4;
				m_regE = m_regE;
				break;
			
			case 0x5C: // ld_e_h  
				cCycles -= 4;
				m_regE = m_regH;
				break;
			
			case 0x5D: // ld_e_l  
				cCycles -= 4;
				m_regE = m_regL;
				break;
			
			case 0x5E: // ld_e_xhl   
				cCycles -= 7;
				m_regE = MemReadByte(m_regHL);
				break;
			
			case 0x5F: // ld_e_a  
				cCycles -= 4;
				m_regE = m_regA;
				break;

			case 0x60: // ld_h_b  
				cCycles -= 4;
				m_regH = m_regB;
				break;
			
			case 0x61: // ld_h_c    
				cCycles -= 4;
				m_regH = m_regC;
				break;
			
			case 0x62: // ld_h_d     
				cCycles -= 4;
				m_regH = m_regD;
				break;
			
			case 0x63: // ld_h_e    
				cCycles -= 4;
				m_regH = m_regE;
				break;
			
			case 0x64: // ld_h_h  
				cCycles -= 4;
				m_regH = m_regH;
				break;
			
			case 0x65: // ld_h_l  
				cCycles -= 4;
				m_regH = m_regL;
				break;
			
			case 0x66: // ld_h_xhl   
				cCycles -= 7;
				m_regH = MemReadByte(m_regHL);
				break;
			
			case 0x67: // ld_h_a  
				cCycles -= 4;
				m_regH = m_regA;
				break;

			case 0x68: // ld_l_b  
				cCycles -= 4;
				m_regL = m_regB;
				break;
			
			case 0x69: // ld_l_c    
				cCycles -= 4;
				m_regL = m_regC;
				break;
			
			case 0x6A: // ld_l_d     
				cCycles -= 4;
				m_regL = m_regD;
				break;
			
			case 0x6B: // ld_l_e    
				cCycles -= 4;
				m_regL = m_regE;
				break;
			
			case 0x6C: // ld_l_h  
				cCycles -= 4;
				m_regL = m_regH;
				break;
			
			case 0x6D: // ld_l_l  
				cCycles -= 4;
				m_regL = m_regL;
				break;
			
			case 0x6E: // ld_l_xhl   
				cCycles -= 7;
				m_regL = MemReadByte(m_regHL);
				break;
			
			case 0x6F: // ld_l_a  
				cCycles -= 4;
				m_regL = m_regA;
				break;

			case 0x70: // ld_xhl_b
				cCycles -= 7;
				MemWriteByte(m_regHL, m_regB);
				break;
			
			case 0x71: // ld_xhl_c  
				cCycles -= 7;
				MemWriteByte(m_regHL, m_regC);
				break;
			
			case 0x72: // ld_xhl_d   
				cCycles -= 7;
				MemWriteByte(m_regHL, m_regD);
				break;
			
			case 0x73: // ld_xhl_e  
				cCycles -= 7;
				MemWriteByte(m_regHL, m_regE);
				break;
			
			case 0x74: // ld_xhl_h
				cCycles -= 7;
				MemWriteByte(m_regHL, m_regH);
				break;
			
			case 0x75: // ld_xhl_l
				cCycles -= 7;
				MemWriteByte(m_regHL, m_regL);
				break;
			
			case 0x76: // halt
				cCycles -= 4;
				SetPC(GetPC() - 1);
				m_fHalt = TRUE;
				goto z80ExecBottom;
				/* return (cCyclesArg - cCycles); */
			
			case 0x77: // ld_xhl_a
				cCycles -= 7;
				MemWriteByte(m_regHL, m_regA);
				break;

			case 0x78: // ld_a_b  
				cCycles -= 4;
				m_regA = m_regB;
				break;
			
			case 0x79: // ld_a_c    
				cCycles -= 4;
				m_regA = m_regC;
				break;
			
			case 0x7A: // ld_a_d     
				cCycles -= 4;
				m_regA = m_regD;
				break;
			
			case 0x7B: // ld_a_e    
				cCycles -= 4;
				m_regA = m_regE;
				break;
			
			case 0x7C: // ld_a_h  
				cCycles -= 4;
				m_regA = m_regH;
				break;
			
			case 0x7D: // ld_a_l  
				cCycles -= 4;
				m_regA = m_regL;
				break;
			
			case 0x7E: // ld_a_xhl   
				cCycles -= 7;
				m_regA = MemReadByte(m_regHL);
				break;
			
			case 0x7F: // ld_a_a  
				cCycles -= 4;
				m_regA = m_regA;
				break;

			case 0x80: // add_a_b 
				cCycles -= 4;
				Add_1(m_regB);
				break;
			
			case 0x81: // add_a_c   
				cCycles -= 4;
				Add_1(m_regC);
				break;
			
			case 0x82: // add_a_d    
				cCycles -= 4;
				Add_1(m_regD);
				break;
			
			case 0x83: // add_a_e   
				cCycles -= 4;
				Add_1(m_regE);
				break;
			
			case 0x84: // add_a_h 
				cCycles -= 4;
				Add_1(m_regH);
				break;
			
			case 0x85: // add_a_l 
				cCycles -= 4;
				Add_1(m_regL);
				break;
			
			case 0x86: // add_a_xhl  
				cCycles -= 7;
				Add_1(MemReadByte(m_regHL));
				break;
			
			case 0x87: // add_a_a 
				cCycles -= 4;
				Add_1(m_regA);
				break;

			case 0x88: // adc_a_b 
				cCycles -= 4;
				Adc_1(m_regB);
				break;
			
			case 0x89: // adc_a_c   
				cCycles -= 4;
				Adc_1(m_regC);
				break;
			
			case 0x8A: // adc_a_d    
				cCycles -= 4;
				Adc_1(m_regD);
				break;
			
			case 0x8B: // adc_a_e   
				cCycles -= 4;
				Adc_1(m_regE);
				break;
			
			case 0x8C: // adc_a_h 
				cCycles -= 4;
				Adc_1(m_regH);
				break;
			
			case 0x8D: // adc_a_l 
				cCycles -= 4;
				Adc_1(m_regL);
				break;
			
			case 0x8E: // adc_a_xhl  
				cCycles -= 7;
				Adc_1(MemReadByte(m_regHL));
				break;
			
			case 0x8F: // adc_a_a 
				cCycles -= 4;
				Adc_1(m_regA);
				break;

			case 0x90: // sub_b   
				cCycles -= 4;
				Sub_1(m_regB);
				break;
			
			case 0x91: // sub_c     
				cCycles -= 4;
				Sub_1(m_regC);
				break;
			
			case 0x92: // sub_d      
				cCycles -= 4;
				Sub_1(m_regD);
				break;
			
			case 0x93: // sub_e     
				cCycles -= 4;
				Sub_1(m_regE);
				break;
			
			case 0x94: // sub_h   
				cCycles -= 4;
				Sub_1(m_regH);
				break;
			
			case 0x95: // sub_l   
				cCycles -= 4;
				Sub_1(m_regL);
				break;
			
			case 0x96: // sub_xhl    
				cCycles -= 7;
				Sub_1(MemReadByte(m_regHL));
				break;
			
			case 0x97: // sub_a   
				cCycles -= 4;
				Sub_1(m_regA);
				break;

			case 0x98: // sbc_a_b 
				cCycles -= 4;
				Sbc_1(m_regB);
				break;
			
			case 0x99: // sbc_a_c   
				cCycles -= 4;
				Sbc_1(m_regC);
				break;
			
			case 0x9A: // sbc_a_d    
				cCycles -= 4;
				Sbc_1(m_regD);
				break;
			
			case 0x9B: // sbc_a_e   
				cCycles -= 4;
				Sbc_1(m_regE);
				break;
			
			case 0x9C: // sbc_a_h 
				cCycles -= 4;
				Sbc_1(m_regH);
				break;
			
			case 0x9D: // sbc_a_l 
				cCycles -= 4;
				Sbc_1(m_regL);
				break;
			
			case 0x9E: // sbc_a_xhl  
				cCycles -= 7;
				Sbc_1(MemReadByte(m_regHL));
				break;
			
			case 0x9F: // sbc_a_a 
				cCycles -= 4;
				Sbc_1(m_regA);
				break;

			case 0xA0: // and_b   
				cCycles -= 4;
				And(m_regB);
				break;
			
			case 0xA1: // and_c     
				cCycles -= 4;
				And(m_regC);
				break;
			
			case 0xA2: // and_d      
				cCycles -= 4;
				And(m_regD);
				break;
			
			case 0xA3: // and_e     
				cCycles -= 4;
				And(m_regE);
				break;
			
			case 0xA4: // and_h   
				cCycles -= 4;
				And(m_regH);
				break;
			
			case 0xA5: // and_l   
				cCycles -= 4;
				And(m_regL);
				break;
			
			case 0xA6: // and_xhl    
				cCycles -= 7;
				And(MemReadByte(m_regHL));
				break;
			
			case 0xA7: // and_a   
				cCycles -= 4;
				And(m_regA);
				break;

			case 0xA8: // xor_b   
				cCycles -= 4;
				Xor(m_regB);
				break;
			
			case 0xA9: // xor_c     
				cCycles -= 4;
				Xor(m_regC);
				break;
			
			case 0xAA: // xor_d      
				cCycles -= 4;
				Xor(m_regD);
				break;
			
			case 0xAB: // xor_e     
				cCycles -= 4;
				Xor(m_regE);
				break;
			
			case 0xAC: // xor_h   
				cCycles -= 4;
				Xor(m_regH);
				break;
			
			case 0xAD: // xor_l   
				cCycles -= 4;
				Xor(m_regL);
				break;
			
			case 0xAE: // xor_xhl    
				cCycles -= 7;
				Xor(MemReadByte(m_regHL));
				break;
			
			case 0xAF: // xor_a   
				cCycles -= 4;
				Xor(m_regA);
				break;

			case 0xB0: // or_b    
				cCycles -= 4;
				Or(m_regB);
				break;
			
			case 0xB1: // or_c      
				cCycles -= 4;
				Or(m_regC);
				break;
			
			case 0xB2: // or_d       
				cCycles -= 4;
				Or(m_regD);
				break;
			
			case 0xB3: // or_e      
				cCycles -= 4;
				Or(m_regE);
				break;
			
			case 0xB4: // or_h    
				cCycles -= 4;
				Or(m_regH);
				break;
			
			case 0xB5: // or_l    
				cCycles -= 4;
				Or(m_regL);
				break;
			
			case 0xB6: // or_xhl     
				cCycles -= 7;
				Or(MemReadByte(m_regHL));
				break;
			
			case 0xB7: // or_a    
				cCycles -= 4;
				Or(m_regA);
				break;

			case 0xB8: // cp_b    
				cCycles -= 4;
				Cp(m_regB);
				break;
			
			case 0xB9: // cp_c      
				cCycles -= 4;
				Cp(m_regC);
				break;
			
			case 0xBA: // cp_d       
				cCycles -= 4;
				Cp(m_regD);
				break;
			
			case 0xBB: // cp_e      
				cCycles -= 4;
				Cp(m_regE);
				break;
			
			case 0xBC: // cp_h    
				cCycles -= 4;
				Cp(m_regH);
				break;
			
			case 0xBD: // cp_l    
				cCycles -= 4;
				Cp(m_regL);
				break;
			
			case 0xBE: // cp_xhl     
				cCycles -= 7;
				Cp(MemReadByte(m_regHL));
				break;
			
			case 0xBF: // cp_a    
				cCycles -= 4;
				Cp(m_regA);
				break;

			case 0xC0: // ret_nz 
				cCycles -= 5;
				cCycles -= Ret1(m_regF & Z_FLAG);
				break;
			
			case 0xC1: // pop_bc    
				cCycles -= 10;
				m_regBC = Pop();
				break;
			
			case 0xC2: // jp_nz      
				cCycles -= 10;
				cCycles -= Jp1(m_regF & Z_FLAG);
				break;
			
			case 0xC3: // jp
				cCycles -= 10;
#if 0
				Jp0(TRUE);
#else
				{
					// speedup hack for Galaga adopted from MAME...
					
					WORD w = ImmedWord();
					WORD wPc = GetPC();
					
					SetPC(w);

					// removed since Galaga never hit it (maybe 1942 will), and it
					// caused the slowdown in Time Pilot and Gyruss hiscore bug
					// it isn't correct anyway since "0085 jp 0088" causes is to return (Gyruss)
					// shouldn't it be if (w == wPC - 3)???
					// jul-26-97 eam

/*
					if (w == wPc)
					{
	//					TRACE(__FILE__ ":jp (infinite loop) at %04X\n", GetPC());
						return (cCyclesArg - cCycles);
					}
					else */
					if (w == wPc - 6) // attn: very Galaga specific!!!! should be done in MageX by patching ROMs with HALTs (once I figure out how to fool the ROM check at bootup)
					{
						if (*m_rgbOpcode == 0x31)
						{
		//					TRACE(__FILE__ ":jp (ld sp,#xxxx) at %04X\n", GetPC());
						  goto z80ExecBottom;
						  /* return (cCyclesArg - cCycles); */
						}
					}
				}
#endif
				break;
			
			case 0xC4: // call_nz 
				cCycles -= 10;
				cCycles -= Call1(m_regF & Z_FLAG);
				break;
			
			case 0xC5: // push_bc
				cCycles -= 11;
				Push(m_regBC);
				break;
			
			case 0xC6: // add_a_byte 
				cCycles -= 7;
				Add_1(ImmedByte());
				break;
			
			case 0xC7: // rst_00  
				cCycles -= 11;
				Rst(0x00);
				break;

			case 0xC8: // ret_z
				cCycles -= 5;
				cCycles -= Ret0(m_regF & Z_FLAG);
				break;
			
			case 0xC9: // ret
				cCycles -= 4;
				cCycles -= Ret0(TRUE);
				break;
			
			case 0xCA: // jp_z
				cCycles -= 10;
				cCycles -= Jp0(m_regF & Z_FLAG);
				break;
			
			case 0xCB: // cb
				cCycles -= HandleCB();
				break;
			
			case 0xCC: // call_z
				cCycles -= 10;
				cCycles -= Call0(m_regF & Z_FLAG);
				break;
			
			case 0xCD: // call
				cCycles -= 10;
				cCycles -= Call0(TRUE);
				break;
			
			case 0xCE: // adc_a_byte
				cCycles -= 7;
				Adc_1(ImmedByte());
				break;
			
			case 0xCF: // rst_08
				cCycles -= 11;
				Rst(0x08);
				break;

			case 0xD0: // ret_nc
				cCycles -= 5;
				cCycles -= Ret1(m_regF & C_FLAG);
				break;
			
			case 0xD1: // pop_de
				cCycles -= 10;
				m_regDE = Pop();
				break;
			
			case 0xD2: // jp_nc
				cCycles -= 10;
				cCycles -= Jp1(m_regF & C_FLAG);
				break;
			
			case 0xD3: // out_byte_a
				cCycles -= 11;
				Out(ImmedByte(), m_regA);
				break;
			
			case 0xD4: // call_nc
				cCycles -= 10;
				cCycles -= Call1(m_regF & C_FLAG);
				break;
			
			case 0xD5: // push_de
				cCycles -= 11;
				Push(m_regDE);
				break;
			
			case 0xD6: // sub_byte
			{
				cCycles -= 7;
				Sub_1(ImmedByte());
				break;
			}
			
			case 0xD7: // rst_10
				cCycles -= 11;
				Rst(0x10);
				break;

			case 0xD8: // ret_c
				cCycles -= 5;
				cCycles -= Ret0(m_regF & C_FLAG);
				break;
			
			case 0xD9: // exx
				cCycles -= 4;
				Exx();
				break;
			
			case 0xDA: // jp_c
				cCycles -= 10;
				cCycles -= Jp0(m_regF & C_FLAG);
				break;