📄 hardware.lst
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00009031 19 D3 F5 02 [R_InterruptStatus] = r1 //
00009033 19 D3 10 70 [P_INT_Ctrl] = r1 //
00009035 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
00009036 40 92 r1 = 0x0000 // 24MHz Fosc
00009037 19 D3 13 70 [P_SystemClock]=r1 // Initial System Clock
00009039 70 92 r1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000903A 19 D3 0B 70 [P_TimerA_Ctrl]=r1 // Initial Timer A
//R1 = 0xfd00 // 16K
0000903C 09 93 ED FC r1 = 0xfced // 15.625K
0000903E 19 D3 0A 70 [P_TimerA_Data]=r1
00009040 09 93 A8 00 r1 = 0x00A8 //
00009042 19 D3 2A 70 [P_DAC_Ctrl] = r1 //
00009044 09 93 FF FF r1 = 0xffff
00009046 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
00009048 11 93 F5 02 R1 = [R_InterruptStatus] //
0000904A 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
0000904C 19 D3 F5 02 [R_InterruptStatus] = r1 //
0000904E 19 D3 10 70 [P_INT_Ctrl] = r1 //
00009050 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
00009051 60 92 r1=0x0020;
00009052 19 D3 13 70 [P_SystemClock]=r1
00009054 09 93 A8 00 r1 = 0x00A8; //
00009056 19 D3 2A 70 [P_DAC_Ctrl]= r1
00009058 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009059 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000905B 09 93 00 FE r1 = 0xfe00; // 24K
0000905D 19 D3 0A 70 [P_TimerA_Data] = r1;
0000905F 09 93 FF FF r1 = 0xffff
00009061 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
00009063 11 93 F5 02 r1 = [R_InterruptStatus] //
00009065 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
00009067 19 D3 F5 02 [R_InterruptStatus] = r1 //
00009069 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000906B 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
0000906C 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000906D 19 D3 13 70 [P_SystemClock] = r1; // Initial System Clock
0000906F 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009070 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
//R1 = 0x0003 // 8K
00009072 40 92 r1 = 0x0000 // Fosc/2
00009073 19 D3 0D 70 [P_TimerB_Ctrl] = r1; // Initial Timer B -> 8192
//R1 = 0xFFFF
00009075 09 93 00 FA r1 = 0xFA00 // Any time for ADPCM channel 0,1
00009077 19 D3 0C 70 [P_TimerB_Data] = r1 // 8K sample rate
00009079 09 93 FF FF r1 = 0xffff
0000907B 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
0000907D 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
0000907E 46 92 r1 = 0x0006
0000907F 19 D3 2A 70 [P_DAC_Ctrl] = r1
00009081 09 93 00 FE r1 = 0xFE00
00009083 19 D3 0A 70 [P_TimerA_Data] = r1 //
00009085 11 93 F5 02 r1 = [R_InterruptStatus] //
00009087 09 A3 10 84 r1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
00009089 19 D3 F5 02 [R_InterruptStatus] = r1 //
0000908B 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000908D 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
0000908E 09 93 A8 00 r1 = 0x00A8
00009090 19 D3 2A 70 [P_DAC_Ctrl] = r1
00009092 09 93 00 FE r1 = 0xFE00
00009094 19 D3 0A 70 [P_TimerA_Data] = r1 //
00009096 11 93 F5 02 r1 = [R_InterruptStatus] //
00009098 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000909A 19 D3 F5 02 [R_InterruptStatus] = r1 //
0000909C 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000909E 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
0000909F 09 93 A8 00 r1 = 0x00A8
000090A1 19 D3 2A 70 [P_DAC_Ctrl] = r1
000090A3 09 93 9A FD r1 = 0xFD9A
000090A5 19 D3 0A 70 [P_TimerA_Data] = r1 //
000090A7 11 93 F5 02 r1 = [R_InterruptStatus] //
000090A9 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000090AB 19 D3 F5 02 [R_InterruptStatus] = r1 //
000090AD 19 D3 10 70 [P_INT_Ctrl] = r1 //
000090AF 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
000090B0 09 93 A8 00 r1 = 0x00A8
000090B2 19 D3 2A 70 [P_DAC_Ctrl] = r1
000090B4 09 93 00 FD r1 = 0xFD00
000090B6 19 D3 0A 70 [P_TimerA_Data] = r1 //
000090B8 11 93 F5 02 r1 = [R_InterruptStatus] //
000090BA 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000090BC 19 D3 F5 02 [R_InterruptStatus] = r1 //
000090BE 19 D3 10 70 [P_INT_Ctrl] = r1 //
000090C0 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
000090C1 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
000090C2 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
000090C4 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000090C5 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
000090C7 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
000090C9 19 D3 0A 70 [P_TimerA_Data] = r1;
000090CB 75 92 r1 = 0x0035; // ADINI should be open (107)
000090CC 19 D3 15 70 [P_ADC_Ctrl] = r1;
000090CE 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
000090D0 19 D3 2A 70 [P_DAC_Ctrl] = r1;
000090D2 09 93 FF FF r1 = 0xffff;
000090D4 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
000090D6 11 93 F5 02 r1 = [R_InterruptStatus] //
000090D8 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
000090DA 19 D3 F5 02 [R_InterruptStatus] = r1 //
000090DC 19 D3 10 70 [P_INT_Ctrl] = r1 //
000090DE 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
000090DF 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
000090E0 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
000090E2 09 93 00 FE r1=0xfe00; //24K @ 24.576MHz
000090E4 19 D3 0A 70 [P_TimerA_Data] = r1
000090E6 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
000090E7 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
000090E8 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
000090EA 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
000090EC 19 D3 0A 70 [P_TimerA_Data] = r1;
000090EE 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
000090EF 90 D4 push r1,r2 to [sp]
000090F0 11 93 17 70 r1=[P_DAC1]
000090F2 09 B3 C0 FF r1 &= ~0x003f
000090F4 09 43 00 80 cmp r1,0x8000
000090F6 0E 0E jb L_RU_NormalUp
000090F7 19 5E je L_RU_End
L_RU_DownLoop:
000090F8 40 F0 5B 91 call F_Delay
000090FA 41 94 r2 = 0x0001
000090FB 1A D5 12 70 [P_Watchdog_Clear] = r2
000090FD 09 23 40 00 r1 -= 0x40
000090FF 19 D3 17 70 [P_DAC1] = r1
00009101 09 43 00 80 cmp r1,0x8000
00009103 4C 4E jne L_RU_DownLoop
L_RD_DownEnd:
00009104 0C EE jmp L_RU_End
L_RU_NormalUp:
L_RU_Loop:
00009105 40 F0 5B 91 call F_Delay
00009107 41 94 r2 = 0x0001
00009108 1A D5 12 70 [P_Watchdog_Clear] = r2
0000910A 09 03 40 00 r1 += 0x40
0000910C 19 D3 17 70 [P_DAC1] = r1
0000910E 09 43 00 80 cmp r1, 0x8000
00009110 4C 4E jne L_RU_Loop
L_RU_End:
00009111 90 90 pop r1,r2 from [sp]
00009112 90 9A retf
.ENDP
//............................................................
_SP_RampDnDAC1: .PROC
F_SP_RampDnDAC1:
00009113 90 D4 push r1,r2 to [sp]
//int off
00009114 11 93 17 70 r1 = [P_DAC1]
00009116 09 B3 C0 FF r1 &= ~0x003F
00009118 0A 5E jz L_RD_End
L_RD_Loop:
00009119 40 F0 5B 91 call F_Delay
0000911B 41 94 r2 = 0x0001
0000911C 1A D5 12 70 [P_Watchdog_Clear] = r2
0000911E 09 23 40 00 r1 -= 0x40
00009120 19 D3 17 70 [P_DAC1] = r1
00009122 4A 4E jnz L_RD_Loop
L_RD_End:
//int fiq,irq
00009123 90 90 pop r1,r2 from [sp]
00009124 90 9A retf
.ENDP
//..............................................................
_SP_RampUpDAC2: .PROC
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