📄 parfpm.lst
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RC51 COMPILER V03.03.29, PARFPM 06/03/03 11:10:04 PAGE 1
QCW(0x00002F32)
WIN32 RC51 COMPILER V03.03.29, COMPILATION OF MODULE PARFPM
OBJECT MODULE PLACED IN d:\data\msc1210\ride\mvp\parfpm.obj
COMPILER INVOKED BY: RC51.EXE D:\DATA\MSC1210\RIDE\MVP\PARFPM.C OBJECT(D:\DATA\M
-SC1210\RIDE\MVP\PARFPM.OBJ) PIN(D:\RIDE\INC) PIN(D:\RIDE\INC\51\TI\
-) NOAM SUE_OPT PR(D:\DATA\MSC1210\RIDE\MVP\PARFPM.LST) CD SB OE(1)
-SM FP(NOFLOAT) PW(80) MAXWAR(200) NOIS UNSIGNEDCHAR ET(CHAR)
stmt level source
1 // Parallel Flash Programming Mode
2 #include <REG1210.H>
3 #include "mvp.h"
WARNING C179 IN LINE 183 OF mvp.h : 'msg' : mspace on parameter ignored
4 SLAVE target;
5 unsigned char fpm(unsigned char cmd, unsigned int a, unsigned cha
-r pd)
6 { unsigned char c,cpu, cmdx,rdcmd;
7 1 // Warning: issues SRD/FRD to both CPUA & CPUS will cause bus con
-flict!!
8 1 cpu=cmd & 0xf0; cmdx=cmd & 0x0f;
9 1 if (cmdx== SRD || cmdx==FRD) {rdcmd=1; P0DDR=P0IDLE; id=0xff;}
10 1 else {P0DDR=P0OUT; id = pd; rdcmd=0;}
11 1 ah= (unsigned char)(a>>8); CMD0 = cmdx &0x01; CP=0; CP=1; CMD1= c
-mdx &0x02;
12 1 al=(unsigned char)a; CMD2= cmdx & 0x04;
13 1 if (cpu==CPUA) { // Aux CPU command
14 2 REQA=1; while(ACKA==0){}; c=(unsigned char)!PASSA;
15 2 if (rdcmd!=0) c=id; else { P0DDR=P0IDLE; id=0xff; }
16 2 REQA=0; while(ACKA==1){};
17 2 } else if (cpu==CPUS) { //Slave CPU command
18 2 REQS=1; while(ACKS==0){}; c=(unsigned char)!PASSS;
19 2 if (rdcmd!=0) c=id; else { P0DDR=P0IDLE; id=0xff; }
20 2 REQS=0; while(ACKS==1){};
21 2 } else if (cpu==CPUBOTH) { //Slave & Aux CPU command
22 2 REQS=1; REQA=1; while(ACKS==0 || ACKA==0){};
23 2 c=(unsigned char)!(PASSS & PASSA); P0DDR=P0IDLE; id=0xff;
24 2 REQS=0; REQA=0; while(ACKS==1 || ACKA==1){};
25 2 } return(c);
26 1 }
27 unsigned char afpm(unsigned char cmd, unsigned int a, unsigned ch
-ar pd)
28 { unsigned char c, rdcmd=0;
29 1 ah= (unsigned char)(a>>8);
30 1 CP=0; CP=1;
31 1 al=(unsigned char)a;
32 1 if (cmd== SRD || cmd==FRD) rdcmd=1; else {P0DDR=P0OUT; id = pd;}
- 33 1 CMD0 = (cmd & 1); CMD1= (cmd>>1) &1; CMD2= (cmd>>2)
-&1;
34 1 REQA=1;
35 1 while(ACKA==0){};
36 1 c=(unsigned char)!PASSA;
37 1 if (rdcmd) c=id; else { P0DDR=P0IDLE; id=0xff; }
38 1 REQA=0;
39 1 while(ACKA==1){};
40 1 return(c);
41 1 }
42 unsigned char sfpm(unsigned char cmd, unsigned int a, unsigned ch
-ar pd)
43 { unsigned char rdcmd=0, err=0;
44 1 if (cmd== SRD || cmd==FRD) {
45 2 rdcmd=1;
46 2 } else {P0DDR=P0OUT; id = pd;}
47 1 ah= (unsigned char)(a>>8);
48 1 CP=0; CP=1;
49 1 al=(unsigned char)a;
50 1 CMD0 = (cmd & 1); CMD1= (cmd>>1) &1; CMD2= (cmd>>2) &1;
51 1 REQS=1;
52 1 t1=100; while(ACKS==0 && t1!=0){}; if (t1==0) err=1;
53 1 if (PASSS==0) err=1;;
54 1 if (rdcmd) err=id; else { P0DDR=P0IDLE; id=0xff; }
55 1 REQS=0;
56 1 t1=100; while(ACKS==1 && t1!=0){}; if (t1==0) err=1;
57 1 return(err);
58 1 }
59 void led(unsigned char color, unsigned char onoff)
60 { unsigned char c;
61 1 c=afpm(SRD,sP3,0);
62 1 if (color==RED && onoff==ON) c &=0xfe;
63 1 else if (color==RED && onoff==OFF) c |=0x01;
64 1 else if (color==GREEN && onoff==ON) c &=0xfd;
65 1 else if (color==GREEN && onoff==OFF) c |=0x02;
66 1 afpm(SWR, sP3, c);
67 1 }
68 void pasel(unsigned char c)
69 { unsigned char k=PASEL;
70 1 if (c==PSEN_PSEN) { k&=0xc7; k|=0x00; } if (c==PSEN_CLK) { k&=0
-xc7; k|=0x10; } if (c==PSEN_MODCLK) { k&=0xc7; k|=0x20; }
71 1 if (c==PSEN_LOW) { k&=0xc7; k|=0x30; } if (c==PSEN_HIGH) { k&=0x
-c7; k|=0x38; }
72 1 if (c==ALE_ALE) { k&=0xfc; k|=0x00; } if (c==ALE_LOW) { k&=0xfc
-; k|=0x02; } if (c==ALE_HIGH) { k&=0xfc; k|=0x03; }
73 1 PASEL=k;
74 1 }
75 void release(void)
76 { pasel(PSEN_LOW);
77 1 ALE=0;
78 1 CMD0=0; CMD1=0; CMD2=0; id=0;
79 1 PASSS=0; PASSA=0; ACKS=0; ACKA=0;
80 1 ah=0; CP=!CP; CP=!CP; al=0;
81 1 MRST=0; REQA=0; REQS=0;
82 1 VDDEN=0;
83 1 }
84 unsigned char resetpfpm(void)
85 { unsigned char err=0;
86 1 unsigned char i;
87 1 MRST=1; REQA=1; VDDEN=1;
88 1 if (SCALE==1) pasel(PSEN_CLK); else pasel(PSEN_PSEN);
89 1 P0DDR=P0IDLE; //P0 GPI
90 1 P1DDR=P1OUT; //P1 GPO
91 1 P2DDR=0;
92 1 P3DDR=0;
93 1 PASSS=1; PASSA=1; ACKS=1; ACKA=1;
94 1 al=0; CP=0; CP=1; // AH=AL=0
95 1 CMD2=0; CMD1=0; CMD0=0;
96 1 REQA=1; REQS=1; ALE=1;
97 1 //P2DDR=0x5144; //P2: OOCO OCOC
98 1 //P3DDR=0x5447; //P3: OOOC OCOI
99 1 t0=50; while(t0!=0 && !high(vdds)){;} // wait 100ms or VDDS ready
-
100 1 t0=50; while(t0!=0 && !(PASSA==1 && PASSS==1 && ACKA==1 && ACKS==
-1 && ALE==1)){;} // wait 100ms or till CPUA&CPUS ready
101 1 if (PASSA==0 || PASSS==0 || ACKA==0 || ACKS==0 || ALE==0) err=1;
- 102 1 ALE=0; // ALE=0, CPUA & CPUS RST => PFPM
103 1 REQA=0; REQS=0;
104 1 MRST=0;
105 1 t0=100; while(ACKA==1 && t0!=0){}; // wait 200ms or ACKA==0
106 1 if (ACKA==1) err=2; // No ACKA from CPUA
107 1 else if (afpm(SRD,sFTCON,0)!=0xA5) err=3; // CPUA SFR read error
- 108 1 i=vdds; if (!high(i)) err=4;
109 1 if (err!=0) {
110 2 putcr(); putstr("\nFatal:");
111 2 if (err==1) putstr("PASS/ACK/ALE line stuck");
112 2 else if (err==2) putstr("No ACKA from CPUA");
113 2 else if (err==3) putstr("CPUA SFR read error");
114 2 else if (err==4) {putstr("Vdds Short circuit at "); tx_hex(i);}
- 115 2 else putstr("Unknown Err");
116 2 release();
117 2 return(err);
118 2 }
119 1 afpm(SWR,sP3DDRL,0x55);
120 1 afpm(SWR,sUSEC,cUSEC); // CPUA timers
121 1 afpm(SWR,sMSECL,(cMSEC & 0xff));
122 1 afpm(SWR,sMSECH,(cMSEC>>8));
123 1 t0=100; while(ACKS==1 && t0!=0){}
124 1 if (sfpm(SRD,sFTCON,0)!=0xA5 || ACKS==1) {
125 2 target.exist=-1;
126 2 } else {
127 2 sfpm(SWR,sUSEC,cUSEC); // CPUS timers
128 2 sfpm(SWR,sMSECL,(cMSEC & 0xff));
129 2 sfpm(SWR,sMSECH,(cMSEC>>8));
130 2 target.HWPC1=sfpm(SRD,sHWPC1,0);
131 2 target.HWPC0=sfpm(SRD,sHWPC0,0);
132 2 target.HWID=sfpm(SRD,sHWID,0);
133 2 target.secure=((sfpm(FRD,0x807f,0)&0x80)==0)?1:0;
134 2 if (target.HWPC1==0 && (target.HWPC0&0x80)==0){ // Found MSC1210
-
135 3 target.exist=1;
136 3 target.part=MSC1210;
137 3 if ((target.HWPC0 & 0x03)==0) {target.kbyte=4; target.y=2;} //
-Y2
138 3 if ((target.HWPC0 & 0x03)==1) {target.kbyte=8; target.y=3;} //
-Y3
139 3 if ((target.HWPC0 & 0x03)==2) {target.kbyte=16; target.y=4;} /
-/Y4
140 3 if ((target.HWPC0 & 0x03)==3) {target.kbyte=32; target.y=5;} /
-/Y5
141 3 }
142 2 else if (target.HWPC1==0x08 && (target.HWPC0&0x80)==0){ // Found
- MSC1211/12
143 3 target.exist=1;
144 3 if ((target.HWPC0 &0x04)==0) target.part=MSC1212; else target.p
-art=MSC1211;
145 3 if ((target.HWPC0 & 0x03)==0) {target.kbyte=4; target.y=2;} //
-Y2
146 3 if ((target.HWPC0 & 0x03)==1) {target.kbyte=8; target.y=3;} //
-Y3
147 3 if ((target.HWPC0 & 0x03)==2) {target.kbyte=16; target.y=4;} /
-/Y4
148 3 if ((target.HWPC0 & 0x03)==3) {target.kbyte=32; target.y=5;} /
-/Y5
149 3 } else target.exist=0; // Device Unknown
150 2 }
151 1 return(err);
152 1 }
153 unsigned char blackout(unsigned int i)
154 { unsigned char c;
155 1 if ((i>>8)==0x80){ // blackout on hex 80xx
156 2 c=i&0x00ff;
157 2 if (c==0 || c==1 || (c>=0x70 && c<=0x7D)) return(1); else return
-(0);
158 2 } else return(0);
159 1 }
160 #define Pass 0
161 #define Fail 1
162 #define P Pass
163 #define F Fail
164 #define RETENTION 0xaa
165 // March Test
166 #define MarchEnd 255
167 #define MarchBeg 0 //4k
168 #define MarchNum 5
169 #define MarchElement 7
170 #define UpDown (MarchElement-1)
171 char march(unsigned char cpu)
172 { long int li=0;
173 1 unsigned char code m[MarchNum][MarchElement]= {
174 1 'w', 0 , 0 , 0 , 0 , 0 ,'U',
175 1 'r','W','R','w','r','W','U',
176 1 'R','w','W', 0 , 0 , 0 ,'U',
177 1 'R','w','W','w', 0 , 0 ,'D',
178 1 'r','W','w', 0 , 0 , 0 ,'D',
179 1 };
WARNING C217 IN LINE 179 OF parfpm.c : 'm' local variable code qualified : 'sta
-tic' assumed
180 1 unsigned char mn, mn_done, me, me_done, p, pg_done, index, index
-_done;
181 1 unsigned char bi,ei,inc,val,op;
182 1 unsigned char c,result, b,e;
183 1 unsigned int pa;
184 1 unsigned char a, trial=0;
185 1 li++;
186 1 result=Pass;
187 1 mn=0; mn_done=0;
188 1 while (!mn_done){
189 2 tx_byte(mn+'0');
190 2 c=m[mn][UpDown];
191 2 if (c=='U') {b=MarchBeg; e=MarchEnd; inc=1; bi=0; ei=127;}
192 2 else {b=MarchEnd; e=MarchBeg; inc=-1; bi=127; ei=0;}
193 2 p=b; pg_done=0;
194 2 while(!pg_done) {
195 3 resetpfpm();
196 3 pa=p*128; me=0; me_done=0;
197 3 if ((p&0x01)==0x01) led(RED,ON);
198 3 if ((p&0x01)==0x00) led(RED,OFF);
199 3 while (!me_done) {
200 4 op=m[mn][me];
201 4 if (op==0 || op=='U' || op=='D') {me_done=1;}
202 4 if (op=='w' || op=='r') val=ZERO; else val=ONE;
203 4 if (op=='w' || op=='W') {
204 5 c=fpm(cpu|FPE,pa, 0x0ff); // erase destination page
205 5 if (c!=0){putstr("ErrFPE: "); result=Fail; pg_done=1; index_d
-one=1; me_done=1; mn_done=1;} else {
206 6 index=bi; index_done=0;
207 6 //putstr("\nER-");tx_hex(pa >> 8); tx_hex(pa);
208 6 }
209 5 while(!index_done){
210 6 c=fpm(cpu|FWR,index+pa,val);
211 6 if (c!=0){
212 7 if (trial>3){
213 8 putstr("ErrFWR: "); result=Fail; pg_done=1; index_done=1;
-me_done=1; mn_done=1;
214 8 } else trial++;
215 7 } else {
216 7 trial=0;
217 7 if (index==ei) index_done=1;
218 7 index +=inc;
219 7 //tx_byte('.');
220 7 }
221 6 }
222 5 }
223 4 if (op=='r' || op=='R') {
224 5 index=bi;
225 5 while(!index_done){
226 6 c=fpm(cpu|FRD,index+pa,0);
227 6 if (c!=val){result=Fail; pg_done=1; index_done=1; me_done=1;
- mn_done=1;} else {
228 7 if (index==ei) index_done=1;
229 7 index +=inc;
230 7 }
231 6 }
232 5 }
233 4 me++;
234 4 if(me==MarchElement) me_done=1;
235 4 }
236 3 if (result==Fail){
237 4 tx_byte(result);
238 4 putstr(" MN="); tx_hex(mn);
239 4 putstr(" ME="); tx_hex(me);
240 4 putstr(" P="); tx_hex(p);
241 4 putstr(" End="); tx_hex(e);
242 4 putstr(" Op="); tx_byte(op);
243 4 putstr(" PA="); tx_hex(pa >> 8); tx_hex(pa);
244 4 putstr(" Idx="); tx_hex(index);
245 4 putstr(" Val="); tx_hex(val); putcr();
246 4 tx_hex(me_done); tx_hex(pg_done); tx_hex(mn_done); putcr();
247 4 }
248 3 if (p==e) pg_done=1;
249 3 p+=inc;
250 3 }
251 2 if (mn==MarchNum) mn_done=1;
252 2 mn++;
253 2
254 2 }
255 1 return(result);
256 1 }
WARNING C092 IN LINE 184 OF parfpm.c : 'a' is declared but not used
257 // System Util
258 // k select tests (any key to stop toggle tests)
259 //00:
260 //01: Secure
261 //02: Copy from src to dest CPU (input cpu)
262 //03: Verify from src to dest CPU (input cpu)
263 //04: Blank check
264 //05: FME
265 //07: Toggle ID
266 //08: Toggle AL
267 //09: Toggle AH
268 //0a: Toggle CMD ReqA ReqS
269 //0b: Continuous Address March for testing address lines
270 //0c: After-bake: Slave Retention Check only
271 //0d: After-bake: Slave Retention Check and March Test
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