📄 reg1210.lst
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RC51 COMPILER V03.03.26, REG1210 07/07/02 01:33:51 PAGE 1
QCW(0x00002F32)
WIN32 RC51 COMPILER V03.03.26, COMPILATION OF MODULE REG1210
OBJECT MODULE PLACED IN d:\data\msc1210\msc1210 daq evm\ride\daqevm\reg1210.obj
-COMPILER INVOKED BY: RC51.EXE D:\DATA\MSC1210\MSC1210 DAQ EVM\RIDE\
-DAQEVM\REG1210.H OBJECT(D:\DATA\MSC1210\MSC1210 DAQ EVM\RIDE\DAQEVM
-\REG1210.OBJ) PIN(D:\RIDE\INC) NOAM PR(D:\DATA\MSC1210\MSC1210 DAQ
-EVM\RIDE\DAQEVM\REG1210.LST) CD SB OE(1) SM MODAMD(DP2) FP(NOFLOAT)
- PW(80) NOIS UNSIGNEDCHAR ET(CHAR)
stmt level source
1 // Texas Instruments
2 // Name: Reg1210.h
3 // Revision: 1.0
4 // Description: Header file for TI MSC1210 microcontroller
5
6 /* BYTE Registers */
7 sfr P0 = 0x80;
8 sfr SP = 0x81;
9 sfr DPL = 0x82;
10 sfr DPH = 0x83;
11 sfr DPL0 = 0x82;
12 sfr DPH0 = 0x83;
13 sfr DPL1 = 0x84;
14 sfr DPH1 = 0x85;
15 sfr DPS = 0x86;
16 sfr PCON = 0x87;
17 sfr TCON = 0x88;
18 sbit TF1 = TCON^7;
19 sbit TR1 = TCON^6;
20 sbit TF0 = TCON^5;
21 sbit TR0 = TCON^4;
22 sbit IE1 = TCON^3;
23 sbit IT1 = TCON^2;
24 sbit IE0 = TCON^1;
25 sbit IT0 = TCON^0;
26 sfr TMOD = 0x89;
27 sfr TL0 = 0x8A;
28 sfr TL1 = 0x8B;
29 sfr TH0 = 0x8C;
30 sfr TH1 = 0x8D;
31 sfr CKCON = 0x8E;
32 sfr MWS = 0x8F;
33 sfr P1 = 0x90;
34 sbit INT5 = P1^7;
35 sbit SCK = P1^7;
36 sbit INT4 = P1^6;
37 sbit MISO = P1^6;
38 sbit INT3 = P1^5;
39 sbit MOSI = P1^5;
40 sbit INT2 = P1^4;
41 sbit SS = P1^4;
42 sbit TXD1 = P1^3;
43 sbit RXD1 = P1^2;
44 sbit T2EX = P1^1;
45 sbit T2 = P1^0;
46 sfr EXIF = 0x91;
47 sfr MPAGE = 0x92;
48 sfr CADDR = 0x93;
49 sfr CDATA = 0x94;
50 sfr MCON = 0x95;
51 sfr SCON = 0x98;
52 sfr SCON0 = 0x98;
53 sbit SM0_0 = SCON0^7;
54 sbit SM1_0 = SCON0^6;
55 sbit SM2_0 = SCON0^5;
56 sbit REN_0 = SCON0^4;
57 sbit TB8_0 = SCON0^3;
58 sbit RB8_0 = SCON0^2;
59 sbit TI_0 = SCON0^1;
60 sbit TI = SCON0^1;
61 sbit RI_0 = SCON0^0;
62 sbit RI = SCON0^0;
63 sfr SBUF = 0x99;
64 sfr SBUF0 = 0x99;
65 sfr SPICON = 0x9A;
66 sfr SPIDATA = 0x9B;
67 sfr SPIRCON = 0x9C;
68 sfr SPITCON = 0x9D;
69 sfr SPISTRT = 0x9E;
70 sfr SPIEND = 0x9F;
71 sfr P2 = 0xA0;
72 sfr PWMCON = 0xA1;
73 sfr PWMLOW = 0xA2;
74 sfr PWMHI = 0xA3;
75 sfr PAI = 0xA5;
76 sfr AIE = 0xA6;
77 sfr AISTAT = 0xA7;
78 sfr IE = 0xA8;
79 sbit EA = IE^7;
80 sbit ES1 = IE^6;
81 sbit ET2 = IE^5;
82 sbit ES0 = IE^4;
83 sbit ET1 = IE^3;
84 sbit EX1 = IE^2;
85 sbit ET0 = IE^1;
86 sbit EX0 = IE^0;
87 sfr BPCON = 0xA9;
88 sfr BPL = 0xAA;
89 sfr BPH = 0xAB;
90 sfr P0DDRL = 0xAC;
91 sfr P0DDRH = 0xAD;
92 sfr P1DDRL = 0xAE;
93 sfr P1DDRH = 0xAF;
94 sfr P3 = 0xB0;
95 sbit RD = P3^7;
96 sbit WR = P3^6;
97 sbit T1 = P3^5;
98 sbit T0 = P3^4;
99 sbit INT1 = P3^3;
100 sbit INT0 = P3^2;
101 sbit TXD = P3^1;
102 sbit TXD0 = P3^1;
103 sbit RXD = P3^0;
104 sbit RXD0 = P3^0;
105 sfr P2DDRL = 0xB1;
106 sfr P2DDRH = 0xB2;
107 sfr P3DDRL = 0xB3;
108 sfr P3DDRH = 0xB4;
109 sfr IP = 0xB8;
110 sbit PS1 = IP^6;
111 sbit PT2 = IP^5;
112 sbit PS = IP^4;
113 sbit PS0 = IP^4;
114 sbit PT1 = IP^3;
115 sbit PX1 = IP^2;
116 sbit PT0 = IP^1;
117 sbit PX0 = IP^0;
118 sfr SCON1 = 0xC0;
119 sbit SM0_1 = SCON1^7;
120 sbit SM1_1 = SCON1^6;
121 sbit SM2_1 = SCON1^5;
122 sbit REN_1 = SCON1^4;
123 sbit TB8_1 = SCON1^3;
124 sbit RB8_1 = SCON1^2;
125 sbit TI_1 = SCON1^1;
126 sbit RI_1 = SCON1^0;
127 sfr SBUF1 = 0xC1;
128 sfr EWU = 0xC6;
129 sfr T2CON = 0xC8;
130 sbit TF2 = T2CON^7;
131 sbit EXF2 = T2CON^6;
132 sbit RCLK = T2CON^5;
133 sbit TCLK = T2CON^4;
134 sbit EXEN2 = T2CON^3;
135 sbit TR2 = T2CON^2;
136 sbit C_T2 = T2CON^1;
137 sbit CP_RL2 = T2CON^0;
138 sfr RCAP2L = 0xCA;
139 sfr RCAP2H = 0xCB;
140 sfr TL2 = 0xCC;
141 sfr TH2 = 0xCD;
142 sfr PSW = 0xD0;
143 sbit CY = PSW^7;
144 sbit AC = PSW^6;
145 sbit F0 = PSW^5;
146 sbit RS1 = PSW^4;
147 sbit RS0 = PSW^3;
148 sbit OV = PSW^2;
149 sbit F1 = PSW^1;
150 sbit P = PSW^0;
151 sfr OCL = 0xD1;
152 sfr OCM = 0xD2;
153 sfr OCH = 0xD3;
154 sfr GCL = 0xD4;
155 sfr GCM = 0xD5;
156 sfr GCH = 0xD6;
157 sfr ADMUX = 0xD7;
158 sfr EICON = 0xD8;
159 sbit SMOD1 = EICON^7;
160 sbit EAI = EICON^5;
161 sbit AI = EICON^4;
162 sbit WDTI = EICON^3;
163 sfr ADRESL = 0xD9;
164 sfr ADRESM = 0xDA;
165 sfr ADRESH = 0xDB;
166 sfr ADCON0 = 0xDC;
167 sfr ADCON1 = 0xDD;
168 sfr ADCON2 = 0xDE;
169 sfr ADCON3 = 0xDF;
170 sfr ACC = 0xE0;
171 sfr SSCON = 0xE1;
172 sfr SUMR0 = 0xE2;
173 sfr SUMR1 = 0xE3;
174 sfr SUMR2 = 0xE4;
175 sfr SUMR3 = 0xE5;
176 sfr ODAC = 0xE6;
177 sfr LVDCON = 0xE7;
178 sfr EIE = 0xE8;
179 sbit EWDI = EIE^4;
180 sbit EX5 = EIE^3;
181 sbit EX4 = EIE^2;
182 sbit EX3 = EIE^1;
183 sbit EX2 = EIE^0;
184 sfr HWPC0 = 0xE9;
185 sfr HWPC1 = 0xEA;
186 sfr HWID = 0xEB;
187 sfr FMCON = 0xEE;
188 sfr FTCON = 0xEF;
189 sfr B = 0xF0;
190 sfr PDCON = 0xF1;
191 sfr PASEL = 0xF2;
192 sfr ACLK = 0xF6;
193 sfr SRST = 0xF7;
194 sfr EIP = 0xF8;
195 sbit PWDI = EIP^4;
196 sbit PX5 = EIP^3;
197 sbit PX4 = EIP^2;
198 sbit PX3 = EIP^1;
199 sbit PX2 = EIP^0;
200 sfr SECINT = 0xF9;
201 sfr MSINT = 0xFA;
202 sfr USEC = 0xFB;
203 sfr MSECL = 0xFC;
204 sfr MSECH = 0xFD;
205 sfr HMSEC = 0xFE;
206 sfr WDTCON = 0xFF;
207
208 /*-----------------*/
209 /* Word Registers */
210 /*-----------------*/
211 sfr16 DECIMATION = 0xde;
212 sfr16 THL2 = 0xcc;
213 sfr16 RCAP2 = 0xca;
214 sfr16 ONEMS = 0xfc;
215 sfr16 PWM = 0xa2;
216 sfr16 P0DDR = 0xac;
217 sfr16 P1DDR = 0xae;
218 sfr16 P2DDR = 0xb1;
219 sfr16 P3DDR = 0xb3;
220 sfr16 BRKPT = 0xaa;
221
RC51 COMPILER V03.03.26, REG1210 07/07/02 01:33:51 PAGE 2
ASSEMBLY LISTING OF GENERATED OBJECT CODE
RC51 COMPILER V03.03.26, REG1210 07/07/02 01:33:51 PAGE 3
NAME CLASS MSPACE TYPE OFFSET SIZE
==== ===== ====== ==== ====== ====
RC51 COMPILER V03.03.26, REG1210 07/07/02 01:33:52 PAGE 4
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
RC51 COMPILATION COMPLETE. 0 WARNING, 0 ERROR
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