sort.out

来自「51的VERILOG代码！适用于Xilinx的FPGA」· OUT 代码 · 共 27 行

Loading snapshot worklib.oc8051_tb:v .................... Done
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
ncsim> run

Warning!  some objects excluded from $dumpvars due to -access -R
            File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16
           Scope: oc8051_tb
            Time: 0 FS + 0

time                    1 step           0: pass
time                69446 step           1: pass
time                70026 step           2: pass
time                70486 step           3: pass
time                70946 step           4: pass
time                71406 step           5: pass
time                71866 step           6: pass
time                72326 step           7: pass
time                72786 step           8: pass
time                73246 step           9: pass
time                73706 step          10: pass
time                74166 step          11: pass

 Done!
Simulation complete via $finish(1) at time 74166 NS + 2
/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155       $finish;
ncsim> exit