ncvlog.out

51的VERILOG代码！适用于Xilinx的FPGA

file: ../../../bench/verilog/oc8051_tb.v
	module worklib.oc8051_tb:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_top.v
	module worklib.oc8051_top:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_alu_src1_sel.v
	module worklib.oc8051_alu_src1_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_alu_src2_sel.v
	module worklib.oc8051_alu_src2_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_alu_src3_sel.v
	module worklib.oc8051_alu_src3_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_alu.v
	module worklib.oc8051_alu:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_decoder.v
	module worklib.oc8051_decoder:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_divide.v
	module worklib.oc8051_divide:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_immediate_sel.v
	module worklib.oc8051_immediate_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_multiply.v
	module worklib.oc8051_multiply:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_op_select.v
	module worklib.oc8051_op_select:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_pc.v
	module worklib.oc8051_pc:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_reg8.v
	module worklib.oc8051_reg8:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_reg2.v
	module worklib.oc8051_reg2:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_reg1.v
	module worklib.oc8051_reg1:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_reg4.v
	module worklib.oc8051_reg4:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_ram_wr_sel.v
	module worklib.oc8051_ram_wr_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_ram_rd_sel.v
	module worklib.oc8051_ram_rd_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_ram_top.v
	module worklib.oc8051_ram_top:v
		errors: 0, warnings: 0
file: ../../../sim/rtl_sim/src/verilog/oc8051_xram.v
	module worklib.oc8051_xram:v
		errors: 0, warnings: 0
file: ../../../sim/rtl_sim/src/verilog/oc8051_ram.v
	module worklib.oc8051_ram:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_acc.v
	module worklib.oc8051_acc:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_comp.v
	module worklib.oc8051_comp:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_sp.v
	module worklib.oc8051_sp:v
		errors: 0, warnings: 0
file: ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v
	module worklib.oc8051_uart_test:v
		errors: 0, warnings: 0
file: ../../../sim/rtl_sim/src/verilog/oc8051_rom.v
	module worklib.oc8051_rom:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_dptr.v
	module worklib.oc8051_dptr:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_cy_select.v
	module worklib.oc8051_cy_select:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_psw.v
	module worklib.oc8051_psw:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_indi_addr.v
	module worklib.oc8051_indi_addr:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_rom_addr_sel.v
	module worklib.oc8051_rom_addr_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_ext_addr_sel.v
	module worklib.oc8051_ext_addr_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_reg3.v
	module worklib.oc8051_reg3:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_ram_sel.v
	module worklib.oc8051_ram_sel:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_ports.v
	module worklib.oc8051_ports:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_b_register.v
	module worklib.oc8051_b_register:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_uart.v
	module worklib.oc8051_uart:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_int.v
	module worklib.oc0851_int:v
		errors: 0, warnings: 0
file: ../../../rtl/verilog/oc8051_tc.v
	module worklib.oc8051_tc:v
		errors: 0, warnings: 0