gcd.out

来自「51的VERILOG代码！适用于Xilinx的FPGA」· OUT 代码 · 共 22 行

Loading snapshot worklib.oc8051_tb:v .................... Done
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
ncsim> run

Warning!  some objects excluded from $dumpvars due to -access -R
            File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16
           Scope: oc8051_tb
            Time: 0 FS + 0

time                    1 step           0: pass
time                 6636 step           1: pass
time                 6826 step           2: pass
time                 7016 step           3: pass
time                 7206 step           4: pass
time                 7396 faulire: mismatch on ports in step           5
 p0_out 03 p1_out 08 p2_out ff
 testvecp 01xxxx
 p_out   0308ff
Simulation complete via $finish(1) at time 7418 NS + 0
/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:146     $finish;
ncsim> exit