sys_ram.vhd

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--Copyright (C) 1991-2002 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only to
--program PLD devices (but not masked PLD devices) from Altera.  Any other
--use of such megafunction design, net list, support information, device
--programming or simulation file, or any other related documentation or
--information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner.  Title to
--the intellectual property, including patents, copyrights, trademarks,
--trade secrets, or maskworks, embodied in any such megafunction design,
--net list, support information, device programming or simulation file, or
--any other related documentation or information provided by Altera or a
--megafunction partner, remains with Altera, the megafunction partner, or
--their respective licensors.  No other licenses, including any licenses
--needed under any third party's intellectual property, are provided herein.
--Copying or modifying any file, or portion thereof, to which this notice
--is attached violates this copyright.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity sys_ram is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal writebyteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

              -- outputs:
                 signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );

end entity sys_ram;


architecture europa of sys_ram is
component sys_ram_lane3_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal rdclken : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal wrclock : IN STD_LOGIC;
                    signal wren : IN STD_LOGIC;

                 -- outputs:
                    signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
                 );
end component sys_ram_lane3_module;

component sys_ram_lane2_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal rdclken : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal wrclock : IN STD_LOGIC;
                    signal wren : IN STD_LOGIC;

                 -- outputs:
                    signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
                 );
end component sys_ram_lane2_module;

component sys_ram_lane1_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal rdclken : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal wrclock : IN STD_LOGIC;
                    signal wren : IN STD_LOGIC;

                 -- outputs:
                    signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
                 );
end component sys_ram_lane1_module;

component sys_ram_lane0_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal rdclken : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal wrclock : IN STD_LOGIC;
                    signal wren : IN STD_LOGIC;

                 -- outputs:
                    signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
                 );
end component sys_ram_lane0_module;

              signal d_lane_0 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal d_lane_1 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal d_lane_2 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal d_lane_3 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal q_lane_0 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal q_lane_1 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal q_lane_2 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal q_lane_3 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal select_all_chunks :  STD_LOGIC;
              signal sys_ram_lane0_address :  STD_LOGIC_VECTOR (5 DOWNTO 0);
              signal sys_ram_lane1_address :  STD_LOGIC_VECTOR (5 DOWNTO 0);
              signal sys_ram_lane2_address :  STD_LOGIC_VECTOR (5 DOWNTO 0);
              signal sys_ram_lane3_address :  STD_LOGIC_VECTOR (5 DOWNTO 0);
              signal write_lane_0 :  STD_LOGIC;
              signal write_lane_1 :  STD_LOGIC;
              signal write_lane_2 :  STD_LOGIC;
              signal write_lane_3 :  STD_LOGIC;

begin

  write_lane_3 <= writebyteenable(3);
  select_all_chunks <= '1';
  sys_ram_lane3_address <= address;
  sys_ram_lane3 : sys_ram_lane3_module
    port map(
      q => q_lane_3,
      wraddress => sys_ram_lane3_address,
      wrclock => clk,
      rdaddress => sys_ram_lane3_address,
      clk => clk,
      rdclken => '1',
      wren => write_lane_3,
      data => d_lane_3,
      reset_n => reset_n
    );


  write_lane_2 <= writebyteenable(2);
  select_all_chunks <= '1';
  sys_ram_lane2_address <= address;
  sys_ram_lane2 : sys_ram_lane2_module
    port map(
      q => q_lane_2,
      wraddress => sys_ram_lane2_address,
      wrclock => clk,
      rdaddress => sys_ram_lane2_address,
      clk => clk,
      rdclken => '1',
      wren => write_lane_2,
      data => d_lane_2,
      reset_n => reset_n
    );


  write_lane_1 <= writebyteenable(1);
  select_all_chunks <= '1';
  sys_ram_lane1_address <= address;
  sys_ram_lane1 : sys_ram_lane1_module
    port map(
      q => q_lane_1,
      wraddress => sys_ram_lane1_address,
      wrclock => clk,
      rdaddress => sys_ram_lane1_address,
      clk => clk,
      rdclken => '1',
      wren => write_lane_1,
      data => d_lane_1,
      reset_n => reset_n
    );


  write_lane_0 <= writebyteenable(0);
  select_all_chunks <= '1';
  sys_ram_lane0_address <= address;
  sys_ram_lane0 : sys_ram_lane0_module
    port map(
      q => q_lane_0,
      wraddress => sys_ram_lane0_address,
      wrclock => clk,
      rdaddress => sys_ram_lane0_address,
      clk => clk,
      rdclken => '1',
      wren => write_lane_0,
      data => d_lane_0,
      reset_n => reset_n
    );


  readdata <= q_lane_3 & q_lane_2 & q_lane_1 & q_lane_0;
  (d_lane_3(7), d_lane_3(6), d_lane_3(5), d_lane_3(4), d_lane_3(3), d_lane_3(2), d_lane_3(1), d_lane_3(0), d_lane_2(7), d_lane_2(6), d_lane_2(5), d_lane_2(4), d_lane_2(3), d_lane_2(2), d_lane_2(1), d_lane_2(0), d_lane_1(7), d_lane_1(6), d_lane_1(5), d_lane_1(4), d_lane_1(3), d_lane_1(2), d_lane_1(1), d_lane_1(0), d_lane_0(7), d_lane_0(6), d_lane_0(5), d_lane_0(4), d_lane_0(3), d_lane_0(2), d_lane_0(1), d_lane_0(0)) <= writedata;

end europa;