nios_module.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

  --registered readdata mux, which is an e_mux
  p1_registered_cpu_data_master_readdata <= Std_Logic_Vector'(A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS)) OR mhz_counter_avalonS_readdata_from_sa;
  --vhdl renameroo for output signals
  cpu_data_master_waitrequest <= internal_cpu_data_master_waitrequest;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_instruction_master_arbitrator is 
        port (
              -- inputs:
                 signal boot_monitor_rom_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_uart_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_uart_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_address : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
                 signal cpu_instruction_master_flush : IN STD_LOGIC;
                 signal cpu_instruction_master_granted_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_granted_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_granted_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_granted_timer_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_granted_uart_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_timer_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_uart_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_read : IN STD_LOGIC;
                 signal cpu_instruction_master_read_data_valid_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_read_data_valid_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_read_data_valid_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_read_data_valid_timer_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_read_data_valid_uart_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_requests_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_requests_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_requests_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_requests_timer_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_requests_uart_s1 : IN STD_LOGIC;
                 signal d1_boot_monitor_rom_s1_end_xfer : IN STD_LOGIC;
                 signal d1_cpu_instruction_master_granted_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal d1_cpu_instruction_master_granted_ext_ram_s1 : IN STD_LOGIC;
                 signal d1_cpu_instruction_master_granted_sys_ram_s1 : IN STD_LOGIC;
                 signal d1_cpu_instruction_master_granted_timer_s1 : IN STD_LOGIC;
                 signal d1_cpu_instruction_master_granted_uart_s1 : IN STD_LOGIC;
                 signal d1_sys_ram_s1_end_xfer : IN STD_LOGIC;
                 signal d1_timer_s1_end_xfer : IN STD_LOGIC;
                 signal d1_tri_state_bridge_avalon_slave_end_xfer : IN STD_LOGIC;
                 signal d1_uart_s1_end_xfer : IN STD_LOGIC;
                 signal d2_reset_n : IN STD_LOGIC;
                 signal incoming_tri_state_bridge_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal sys_ram_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal timer_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal uart_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal cpu_instruction_master_flush_qualified_exported : OUT STD_LOGIC;
                 signal cpu_instruction_master_latency_counter : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal cpu_instruction_master_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal cpu_instruction_master_readdatavalid : OUT STD_LOGIC;
                 signal cpu_instruction_master_waitrequest : OUT STD_LOGIC
              );

attribute auto_dissolve : boolean ;
attribute auto_dissolve of cpu_instruction_master_arbitrator : entity is FALSE ;
end entity cpu_instruction_master_arbitrator;


architecture europa of cpu_instruction_master_arbitrator is
              signal boot_monitor_rom_s1_readdata_from_sa_part_selected_by_negative_dbs :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal cpu_instruction_master_flush_qualified :  STD_LOGIC;
              signal cpu_instruction_master_waitrequest_delayed :  STD_LOGIC;
              signal dummy_sink :  STD_LOGIC;
              signal incoming_tri_state_bridge_data_part_selected_by_negative_dbs :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal internal_cpu_instruction_master_latency_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
              signal internal_cpu_instruction_master_waitrequest :  STD_LOGIC;
              signal latency_load_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
              signal p1_cpu_instruction_master_latency_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
              signal p1_selecto_1_2 :  STD_LOGIC;
              signal pre_flush_cpu_instruction_master_readdatavalid :  STD_LOGIC;
              signal r_0 :  STD_LOGIC;
              signal selecto_1_1 :  STD_LOGIC;
              signal selecto_1_2 :  STD_LOGIC;
              signal sys_ram_s1_readdata_from_sa_part_selected_by_negative_dbs :  STD_LOGIC_VECTOR (15 DOWNTO 0);

begin

  --r_0 cascaded wait assignment, which is an e_assign
  r_0 <= ((((((((((((cpu_instruction_master_qualified_request_sys_ram_s1 OR NOT cpu_instruction_master_requests_sys_ram_s1)) AND ((NOT cpu_instruction_master_qualified_request_sys_ram_s1 OR ((cpu_instruction_master_qualified_request_sys_ram_s1 AND ((NOT cpu_data_master_qualified_request_sys_ram_s1 OR ((cpu_data_master_qualified_request_sys_ram_s1 AND (A_WE_StdLogic ((d1_sys_ram_s1_end_xfer = '1'),(NOT cpu_data_master_s_turn_at_sys_ram_s1),d1_cpu_instruction_master_granted_sys_ram_s1))))))))))) AND ((cpu_instruction_master_qualified_request_boot_monitor_rom_s1 OR NOT cpu_instruction_master_requests_boot_monitor_rom_s1))) AND ((NOT cpu_instruction_master_qualified_request_boot_monitor_rom_s1 OR ((cpu_instruction_master_qualified_request_boot_monitor_rom_s1 AND ((NOT cpu_data_master_qualified_request_boot_monitor_rom_s1 OR ((cpu_data_master_qualified_request_boot_monitor_rom_s1 AND (A_WE_StdLogic ((d1_boot_monitor_rom_s1_end_xfer = '1'),(NOT cpu_data_master_s_turn_at_boot_monitor_rom_s1),d1_cpu_instruction_master_granted_boot_monitor_rom_s1))))))))))) AND ((cpu_instruction_master_qualified_request_ext_ram_s1 OR NOT cpu_instruction_master_requests_ext_ram_s1))) AND ((NOT cpu_instruction_master_qualified_request_ext_ram_s1 OR ((cpu_instruction_master_qualified_request_ext_ram_s1 AND ((NOT cpu_data_master_qualified_request_ext_ram_s1 OR ((cpu_data_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic ((d1_tri_state_bridge_avalon_slave_end_xfer = '1'),(NOT cpu_data_master_s_turn_at_ext_ram_s1),d1_cpu_instruction_master_granted_ext_ram_s1))))))))))) AND ((cpu_instruction_master_qualified_request_timer_s1 OR NOT cpu_instruction_master_requests_timer_s1))) AND ((NOT cpu_instruction_master_qualified_request_timer_s1 OR ((cpu_instruction_master_qualified_request_timer_s1 AND ((NOT cpu_data_master_qualified_request_timer_s1 OR ((cpu_data_master_qualified_request_timer_s1 AND (A_WE_StdLogic ((d1_timer_s1_end_xfer = '1'),(NOT cpu_data_master_s_turn_at_timer_s1),d1_cpu_instruction_master_granted_timer_s1))))))))))) AND ((((NOT cpu_instruction_master_qualified_request_timer_s1 OR NOT cpu_instruction_master_read) OR ((NOT d1_timer_s1_end_xfer AND cpu_instruction_master_read)))))) AND ((cpu_instruction_master_qualified_request_uart_s1 OR NOT cpu_instruction_master_requests_uart_s1))) AND ((NOT cpu_instruction_master_qualified_request_uart_s1 OR ((cpu_instruction_master_qualified_request_uart_s1 AND ((NOT cpu_data_master_qualified_request_uart_s1 OR ((cpu_data_master_qualified_request_uart_s1 AND (A_WE_StdLogic ((d1_uart_s1_end_xfer = '1'),(NOT cpu_data_master_s_turn_at_uart_s1),d1_cpu_instruction_master_granted_uart_s1))))))))))) AND ((((NOT cpu_instruction_master_qualified_request_uart_s1 OR NOT cpu_instruction_master_read) OR ((NOT d1_uart_s1_end_xfer AND cpu_instruction_master_read)))));
  --cascaded wait assignment, which is an e_assign
  internal_cpu_instruction_master_waitrequest <= NOT r_0;
  --dummy sink, which is an e_mux
  dummy_sink <= Vector_To_Std_Logic((((((((((((((((((((((((((cpu_instruction_master_address OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_requests_sys_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_qualified_request_sys_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_sys_ram_s1_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_granted_sys_ram_s1))) OR cpu_instruction_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_requests_boot_monitor_rom_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_qualified_request_boot_monitor_rom_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_boot_monitor_rom_s1_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_granted_boot_monitor_rom_s1))) OR cpu_instruction_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_requests_ext_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_qualified_request_ext_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_tri_state_bridge_avalon_slave_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_granted_ext_ram_s1))) OR cpu_instruction_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_requests_timer_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_qualified_request_timer_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_timer_s1_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_granted_timer_s1))) OR cpu_instruction_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_requests_uart_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_qualified_request_uart_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_uart_s1_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_instruction_master_granted_uart_s1)))));
  --latent slave read data valids which may be flushed, which is an e_mux
  pre_flush_cpu_instruction_master_readdatavalid <= (cpu_instruction_master_read_data_valid_sys_ram_s1 OR cpu_instruction_master_read_data_valid_boot_monitor_rom_s1) OR cpu_instruction_master_read_data_valid_ext_ram_s1;
  --run delay, which is an e_register
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      cpu_instruction_master_waitrequest_delayed <= NOT '0';
    elsif clk'event and clk = '1' then
      if true then 
        cpu_instruction_master_waitrequest_delayed <= internal_cpu_instruction_master_waitrequest;
      end if;
    end if;

  end process;

  --The Flushificator, which is an e_assign
  cpu_instruction_master_flush_qualified <= cpu_instruction_master_flush AND NOT cpu_instruction_master_waitrequest_delayed;
  --latent slave read data valid which is not flushed, which is an e_mux
  cpu_instruction_master_readdatavalid <= (((((((pre_flush_cpu_instruction_master_readdatavalid AND NOT cpu_instruction_master_flush_qualified)) OR ((pre_flush_cpu_instruction_master_readdatavalid AND NOT cpu_instruction_master_flush_qualified))) OR ((pre_flush_cpu_instruction_master_readdatavalid AND NOT cpu_instruction_master_flush_qualified))) OR ((pre_flush_cpu_instruction_master_readdatavalid AND