nios_module.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

              -- inputs:
                 signal boot_monitor_rom_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal cpu_data_master_address : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
                 signal cpu_data_master_granted_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_mhz_counter_avalonS : IN STD_LOGIC;
                 signal cpu_data_master_granted_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_uart_s1 : IN STD_LOGIC;
                 signal cpu_data_master_granted_watchdog_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_mhz_counter_avalonS : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_uart_s1 : IN STD_LOGIC;
                 signal cpu_data_master_qualified_request_watchdog_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_read : IN STD_LOGIC;
                 signal cpu_data_master_read_data_valid_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_data_master_read_data_valid_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_read_data_valid_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_mhz_counter_avalonS : IN STD_LOGIC;
                 signal cpu_data_master_requests_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_uart_s1 : IN STD_LOGIC;
                 signal cpu_data_master_requests_watchdog_pio_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_timer_s1 : IN STD_LOGIC;
                 signal cpu_data_master_s_turn_at_uart_s1 : IN STD_LOGIC;
                 signal cpu_data_master_write : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_ext_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_sys_ram_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_timer_s1 : IN STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_uart_s1 : IN STD_LOGIC;
                 signal d1_boot_monitor_rom_s1_end_xfer : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_ext_ram_s1 : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_sys_ram_s1 : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_timer_s1 : IN STD_LOGIC;
                 signal d1_cpu_data_master_granted_uart_s1 : IN STD_LOGIC;
                 signal d1_mhz_counter_avalonS_end_xfer : IN STD_LOGIC;
                 signal d1_sys_ram_s1_end_xfer : IN STD_LOGIC;
                 signal d1_timer_s1_end_xfer : IN STD_LOGIC;
                 signal d1_tri_state_bridge_avalon_slave_end_xfer : IN STD_LOGIC;
                 signal d1_uart_s1_end_xfer : IN STD_LOGIC;
                 signal d1_watchdog_pio_s1_end_xfer : IN STD_LOGIC;
                 signal d2_reset_n : IN STD_LOGIC;
                 signal incoming_tri_state_bridge_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal mhz_counter_avalonS_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal registered_cpu_data_master_read_data_valid_boot_monitor_rom_s1 : IN STD_LOGIC;
                 signal registered_cpu_data_master_read_data_valid_ext_ram_s1 : IN STD_LOGIC;
                 signal registered_cpu_data_master_read_data_valid_sys_ram_s1 : IN STD_LOGIC;
                 signal sys_ram_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal timer_s1_irq_from_sa : IN STD_LOGIC;
                 signal timer_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal uart_s1_irq_from_sa : IN STD_LOGIC;
                 signal uart_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal cpu_data_master_irq : OUT STD_LOGIC;
                 signal cpu_data_master_irqnumber : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
                 signal cpu_data_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_data_master_reset_n : OUT STD_LOGIC;
                 signal cpu_data_master_waitrequest : OUT STD_LOGIC
              );

attribute auto_dissolve : boolean ;
attribute auto_dissolve of cpu_data_master_arbitrator : entity is FALSE ;
end entity cpu_data_master_arbitrator;


architecture europa of cpu_data_master_arbitrator is
              signal dummy_sink :  STD_LOGIC;
              signal internal_cpu_data_master_waitrequest :  STD_LOGIC;
              signal p1_cpu_data_master_waitrequest :  STD_LOGIC;
              signal p1_registered_cpu_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
              signal r_0 :  STD_LOGIC;
              signal registered_cpu_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  --r_0 cascaded wait assignment, which is an e_assign
  r_0 <= (((((((((((((((cpu_data_master_qualified_request_sys_ram_s1 OR registered_cpu_data_master_read_data_valid_sys_ram_s1) OR NOT cpu_data_master_requests_sys_ram_s1)) AND ((NOT cpu_data_master_qualified_request_sys_ram_s1 OR ((cpu_data_master_qualified_request_sys_ram_s1 AND ((NOT cpu_instruction_master_qualified_request_sys_ram_s1 OR ((cpu_instruction_master_qualified_request_sys_ram_s1 AND (A_WE_StdLogic ((d1_sys_ram_s1_end_xfer = '1'),cpu_data_master_s_turn_at_sys_ram_s1,d1_cpu_data_master_granted_sys_ram_s1))))))))))) AND ((((NOT cpu_data_master_qualified_request_sys_ram_s1 OR NOT cpu_data_master_read) OR ((registered_cpu_data_master_read_data_valid_sys_ram_s1 AND cpu_data_master_read)))))) AND (((cpu_data_master_qualified_request_boot_monitor_rom_s1 OR registered_cpu_data_master_read_data_valid_boot_monitor_rom_s1) OR NOT cpu_data_master_requests_boot_monitor_rom_s1))) AND ((NOT cpu_data_master_qualified_request_boot_monitor_rom_s1 OR ((cpu_data_master_qualified_request_boot_monitor_rom_s1 AND ((NOT cpu_instruction_master_qualified_request_boot_monitor_rom_s1 OR ((cpu_instruction_master_qualified_request_boot_monitor_rom_s1 AND (A_WE_StdLogic ((d1_boot_monitor_rom_s1_end_xfer = '1'),cpu_data_master_s_turn_at_boot_monitor_rom_s1,d1_cpu_data_master_granted_boot_monitor_rom_s1))))))))))) AND ((((NOT cpu_data_master_qualified_request_boot_monitor_rom_s1 OR NOT cpu_data_master_read) OR ((registered_cpu_data_master_read_data_valid_boot_monitor_rom_s1 AND cpu_data_master_read)))))) AND (((cpu_data_master_qualified_request_ext_ram_s1 OR registered_cpu_data_master_read_data_valid_ext_ram_s1) OR NOT cpu_data_master_requests_ext_ram_s1))) AND ((NOT cpu_data_master_qualified_request_ext_ram_s1 OR ((cpu_data_master_qualified_request_ext_ram_s1 AND ((NOT cpu_instruction_master_qualified_request_ext_ram_s1 OR ((cpu_instruction_master_qualified_request_ext_ram_s1 AND (A_WE_StdLogic ((d1_tri_state_bridge_avalon_slave_end_xfer = '1'),cpu_data_master_s_turn_at_ext_ram_s1,d1_cpu_data_master_granted_ext_ram_s1))))))))))) AND ((((NOT cpu_data_master_qualified_request_ext_ram_s1 OR NOT cpu_data_master_read) OR ((registered_cpu_data_master_read_data_valid_ext_ram_s1 AND cpu_data_master_read)))))) AND ((cpu_data_master_qualified_request_timer_s1 OR NOT cpu_data_master_requests_timer_s1))) AND ((NOT cpu_data_master_qualified_request_timer_s1 OR ((cpu_data_master_qualified_request_timer_s1 AND ((NOT cpu_instruction_master_qualified_request_timer_s1 OR ((cpu_instruction_master_qualified_request_timer_s1 AND (A_WE_StdLogic ((d1_timer_s1_end_xfer = '1'),cpu_data_master_s_turn_at_timer_s1,d1_cpu_data_master_granted_timer_s1))))))))))) AND ((NOT cpu_data_master_qualified_request_uart_s1 OR ((cpu_data_master_qualified_request_uart_s1 AND ((NOT cpu_instruction_master_qualified_request_uart_s1 OR ((cpu_instruction_master_qualified_request_uart_s1 AND (A_WE_StdLogic ((d1_uart_s1_end_xfer = '1'),cpu_data_master_s_turn_at_uart_s1,d1_cpu_data_master_granted_uart_s1))))))))))) AND ((cpu_data_master_qualified_request_mhz_counter_avalonS OR NOT cpu_data_master_requests_mhz_counter_avalonS))) AND ((cpu_data_master_qualified_request_watchdog_pio_s1 OR NOT cpu_data_master_requests_watchdog_pio_s1));
  --cascaded wait assignment, which is an e_assign
  p1_cpu_data_master_waitrequest <= NOT r_0;
  --dummy sink, which is an e_mux
  dummy_sink <= Vector_To_Std_Logic(((((((((((((((((((((((((((((((((((((((cpu_data_master_address OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_read_data_valid_sys_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_requests_sys_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_qualified_request_sys_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_sys_ram_s1_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_granted_sys_ram_s1))) OR cpu_data_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_read_data_valid_boot_monitor_rom_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_requests_boot_monitor_rom_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_qualified_request_boot_monitor_rom_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_boot_monitor_rom_s1_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_granted_boot_monitor_rom_s1))) OR cpu_data_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_read_data_valid_ext_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_requests_ext_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_qualified_request_ext_ram_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_tri_state_bridge_avalon_slave_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_granted_ext_ram_s1))) OR cpu_data_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_requests_timer_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_qualified_request_timer_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_timer_s1_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_granted_timer_s1))) OR cpu_data_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_requests_uart_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_qualified_request_uart_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_uart_s1_end_xfer))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_granted_uart_s1))) OR cpu_data_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_requests_mhz_counter_avalonS))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_qualified_request_mhz_counter_avalonS))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_granted_mhz_counter_avalonS))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_mhz_counter_avalonS_end_xfer))) OR cpu_data_master_address) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_requests_watchdog_pio_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_qualified_request_watchdog_pio_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(cpu_data_master_granted_watchdog_pio_s1))) OR ("00000000000000000000" & A_TOSTDLOGICVECTOR(d1_watchdog_pio_s1_end_xfer)))));
  --run register, which is an e_register
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      internal_cpu_data_master_waitrequest <= NOT '0';
    elsif clk'event and clk = '1' then
      if true then 
        internal_cpu_data_master_waitrequest <= NOT (A_WE_StdLogic ((((NOT ((cpu_data_master_read OR cpu_data_master_write)))) = '1'),'0',((NOT p1_cpu_data_master_waitrequest AND internal_cpu_data_master_waitrequest))));
      end if;
    end if;

  end process;

  --cpu/data_master readdata mux, which is an e_mux
  cpu_data_master_readdata <= ((((((Std_Logic_Vector'(A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_sys_ram_s1)) OR sys_ram_s1_readdata_from_sa)) AND ((Std_Logic_Vector'(A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_boot_monitor_rom_s1)) OR boot_monitor_rom_s1_readdata_from_sa))) AND ((Std_Logic_Vector'(A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_ext_ram_s1)) OR incoming_tri_state_bridge_data))) AND ((Std_Logic_Vector'(A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_timer_s1)) OR ("0000000000000000" & timer_s1_readdata_from_sa)))) AND ((Std_Logic_Vector'(A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1) & A_ToStdLogicVector(NOT cpu_data_master_requests_uart_s1)) OR ("0000000000000000" & uart_s1_readdata_from_sa)))) AND ((Std_Logic_Vector'(A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS) & A_ToStdLogicVector(NOT cpu_data_master_requests_mhz_counter_avalonS)) OR registered_cpu_data_master_readdata));
  --reset assignment, which is an e_assign
  cpu_data_master_reset_n <= d2_reset_n;
  --irq mux, which is an e_mux
  cpu_data_master_irq <= timer_s1_irq_from_sa OR uart_s1_irq_from_sa;
  --mux cpu/data_master irqnumber, which is an e_mux
  cpu_data_master_irqnumber <= A_WE_StdLogicVector ((uart_s1_irq_from_sa = '1'),"010000","010001");
  --unpredictable registered wait state incoming data, which is an e_register
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      registered_cpu_data_master_readdata <= "00000000000000000000000000000000";
    elsif clk'event and clk = '1' then
      if true then 
        registered_cpu_data_master_readdata <= p1_registered_cpu_data_master_readdata;
      end if;
    end if;

  end process;