nios_module.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

  --vhdl renameroo for output signals
  cpu_instruction_master_granted_sys_ram_s1 <= internal_cpu_instruction_master_granted_sys_ram_s1;
  --vhdl renameroo for output signals
  d1_cpu_data_master_granted_sys_ram_s1 <= internal_d1_cpu_data_master_granted_sys_ram_s1;
  --vhdl renameroo for output signals
  cpu_data_master_granted_sys_ram_s1 <= internal_cpu_data_master_granted_sys_ram_s1;
  --vhdl renameroo for output signals
  d1_cpu_instruction_master_granted_sys_ram_s1 <= internal_d1_cpu_instruction_master_granted_sys_ram_s1;
  --vhdl renameroo for output signals
  cpu_data_master_qualified_request_sys_ram_s1 <= internal_cpu_data_master_qualified_request_sys_ram_s1;
  --vhdl renameroo for output signals
  cpu_data_master_requests_sys_ram_s1 <= internal_cpu_data_master_requests_sys_ram_s1;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity MUL_cpu_s1_arbitrator is 
        port (
              -- inputs:
                 signal MUL_cpu_s1_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal cpu_custom_instruction_master_clk_en : IN STD_LOGIC;
                 signal cpu_custom_instruction_master_dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_custom_instruction_master_datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_custom_instruction_master_reset : IN STD_LOGIC;
                 signal cpu_custom_instruction_master_start : IN STD_LOGIC_VECTOR (5 DOWNTO 0);

              -- outputs:
                 signal MUL_cpu_s1_clk_en : OUT STD_LOGIC;
                 signal MUL_cpu_s1_dataa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal MUL_cpu_s1_datab : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal MUL_cpu_s1_reset : OUT STD_LOGIC;
                 signal MUL_cpu_s1_result_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal MUL_cpu_select : OUT STD_LOGIC
              );

attribute auto_dissolve : boolean ;
attribute auto_dissolve of MUL_cpu_s1_arbitrator : entity is FALSE ;
end entity MUL_cpu_s1_arbitrator;


architecture europa of MUL_cpu_s1_arbitrator is
              signal MUL_cpu_ci_cycle_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
              signal MUL_cpu_ci_reset_n :  STD_LOGIC;

begin

  MUL_cpu_s1_clk_en <= cpu_custom_instruction_master_clk_en;
  MUL_cpu_s1_reset <= cpu_custom_instruction_master_reset;
  MUL_cpu_s1_dataa <= cpu_custom_instruction_master_dataa (15 DOWNTO 0);
  MUL_cpu_s1_datab <= cpu_custom_instruction_master_datab (15 DOWNTO 0);
  --MUL_cpu local reset_n, which is an e_assign
  MUL_cpu_ci_reset_n <= NOT cpu_custom_instruction_master_reset;
  --MUL_cpu cycle counter, which is an e_register
  process (clk, MUL_cpu_ci_reset_n)
  begin
    if MUL_cpu_ci_reset_n = '0' then
      MUL_cpu_ci_cycle_counter <= "00";
    elsif clk'event and clk = '1' then
      if cpu_custom_instruction_master_clk_en = '1' then 
        MUL_cpu_ci_cycle_counter <= Std_Logic_Vector'(A_ToStdLogicVector(cpu_custom_instruction_master_start(5)) & A_ToStdLogicVector(MUL_cpu_ci_cycle_counter(1)));
      end if;
    end if;

  end process;

  --ci cycle increment, which is an e_assign
  MUL_cpu_select <= cpu_custom_instruction_master_start(5) OR (or_reduce(MUL_cpu_ci_cycle_counter));
  --assign MUL_cpu_s1_result_from_sa = MUL_cpu_s1_result so that symbol knows where to group signals which may go to master only, which is an e_assign
  MUL_cpu_s1_result_from_sa <= MUL_cpu_s1_result;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_custom_instruction_master_arbitrator is 
        port (
              -- inputs:
                 signal MUL_cpu_s1_result_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal MUL_cpu_select : IN STD_LOGIC;
                 signal USR0_cpu_s1_result_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal USR0_cpu_select : IN STD_LOGIC;

              -- outputs:
                 signal cpu_custom_instruction_master_result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );

attribute auto_dissolve : boolean ;
attribute auto_dissolve of cpu_custom_instruction_master_arbitrator : entity is FALSE ;
end entity cpu_custom_instruction_master_arbitrator;


architecture europa of cpu_custom_instruction_master_arbitrator is

begin

  --result mux, which is an e_mux
  cpu_custom_instruction_master_result <= ((Std_Logic_Vector'(A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select) & A_ToStdLogicVector(MUL_cpu_select)) AND MUL_cpu_s1_result_from_sa)) OR ((Std_Logic_Vector'(A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select) & A_ToStdLogicVector(USR0_cpu_select)) AND USR0_cpu_s1_result_from_sa));

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_data_master_arbitrator is 
        port (