nios_module.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

      cpu_data_master_read_data_valid_sys_ram_s1_shift_register <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        cpu_data_master_read_data_valid_sys_ram_s1_shift_register <= p1_cpu_data_master_read_data_valid_sys_ram_s1_shift_register;
      end if;
    end if;

  end process;

  cpu_data_master_read_data_valid_sys_ram_s1 <= cpu_data_master_read_data_valid_sys_ram_s1_shift_register;
  --sys_ram_s1_writedata mux, which is an e_mux
  sys_ram_s1_writedata <= cpu_data_master_writedata;
  internal_cpu_instruction_master_requests_sys_ram_s1 <= to_std_logic(((cpu_instruction_master_address(20 DOWNTO 8) & "00000000") = "000000000010000000000")) AND cpu_instruction_master_read;
  internal_cpu_instruction_master_qualified_request_sys_ram_s1 <= internal_cpu_instruction_master_requests_sys_ram_s1 AND to_std_logic(NOT (("01" < cpu_instruction_master_latency_counter)));
  cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register_in <= (internal_cpu_instruction_master_granted_sys_ram_s1 AND cpu_instruction_master_read) AND NOT sys_ram_s1_waits_for_read;
  p1_cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register <= A_WE_StdLogic ((cpu_instruction_master_flush_qualified_exported = '1'),cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register_in,Vector_To_Std_Logic(Std_Logic_Vector'(A_ToStdLogicVector(cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register) & A_ToStdLogicVector(cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register_in))));
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register <= p1_cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register;
      end if;
    end if;

  end process;

  cpu_instruction_master_read_data_valid_sys_ram_s1 <= cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register;
  --arbitration next grant 0 assignment, which is an e_assign
  next_grant_0 <= A_WE_StdLogic ((grant_0 = '1'),'0',(grant_0 XOR '1'));
  --sys_ram_s1_end_xfer assignment, which is an e_assign
  sys_ram_s1_end_xfer <= NOT ((sys_ram_s1_waits_for_read OR sys_ram_s1_waits_for_write));
  --cpu/data_master gets granted 1
  --out of 2 times contention occurs
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      grant_0 <= '0';
    elsif clk'event and clk = '1' then
      if ((((((((sys_ram_s1_end_xfer AND internal_cpu_data_master_qualified_request_sys_ram_s1) AND internal_cpu_instruction_master_qualified_request_sys_ram_s1))))))) = '1' then 
        grant_0 <= next_grant_0;
      end if;
    end if;

  end process;

  --cpu/data_master wins sys_ram/s1 at begin_xfer, which is an e_register
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      internal_cpu_data_master_s_turn_at_sys_ram_s1 <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        internal_cpu_data_master_s_turn_at_sys_ram_s1 <= to_std_logic((grant_0 < '1'));
      end if;
    end if;

  end process;

  --d1_sys_ram_s1_end_xfer register, which is an e_register
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      internal_d1_sys_ram_s1_end_xfer <= '1';
    elsif clk'event and clk = '1' then
      if true then 
        internal_d1_sys_ram_s1_end_xfer <= sys_ram_s1_end_xfer;
      end if;
    end if;

  end process;

  --d1_cpu_data_master_granted_sys_ram_s1 register granted, which is an e_register
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      internal_d1_cpu_data_master_granted_sys_ram_s1 <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        internal_d1_cpu_data_master_granted_sys_ram_s1 <= internal_cpu_data_master_granted_sys_ram_s1;
      end if;
    end if;

  end process;

  --d1_cpu_instruction_master_granted_sys_ram_s1 register granted, which is an e_register
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then
      internal_d1_cpu_instruction_master_granted_sys_ram_s1 <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        internal_d1_cpu_instruction_master_granted_sys_ram_s1 <= internal_cpu_instruction_master_granted_sys_ram_s1;
      end if;
    end if;

  end process;

  --sys_ram_s1_address mux, which is an e_mux
  sys_ram_s1_address <= A_WE_StdLogicVector ((internal_cpu_data_master_granted_sys_ram_s1 = '1'),EXT ((A_SRL(cpu_data_master_address, 2)), 6),EXT ((A_SRL(cpu_instruction_master_address, 2)), 6));
  --sys_ram_s1_dummy_write assignment, which is an e_mux
  sys_ram_s1_dummy_write <= internal_cpu_data_master_granted_sys_ram_s1 AND cpu_data_master_write;
  sys_ram_s1_waits_for_read <= sys_ram_s1_in_a_read_cycle AND '0';
  --sys_ram_s1_in_a_read_cycle assignment, which is an e_assign
  sys_ram_s1_in_a_read_cycle <= ((internal_cpu_data_master_granted_sys_ram_s1 AND cpu_data_master_read)) OR ((internal_cpu_instruction_master_granted_sys_ram_s1 AND cpu_instruction_master_read));
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= sys_ram_s1_in_a_read_cycle;
  sys_ram_s1_waits_for_write <= sys_ram_s1_in_a_write_cycle AND '0';
  --sys_ram_s1_in_a_write_cycle assignment, which is an e_assign
  sys_ram_s1_in_a_write_cycle <= internal_cpu_data_master_granted_sys_ram_s1 AND cpu_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= sys_ram_s1_in_a_write_cycle;
  wait_for_sys_ram_s1_counter <= '0';
  --sys_ram_s1_writebyteenable qualified byte write enables, which is an e_mux
  sys_ram_s1_writebyteenable <= A_WE_StdLogicVector ((sys_ram_s1_dummy_write = '1'),sys_ram_s1_writebyteenable_sys_ram_s1_pre_write_qualification,"0000");
  --sys_ram_s1_writebyteenable_sys_ram_s1_pre_write_qualification mux, which is an e_mux
  sys_ram_s1_writebyteenable_sys_ram_s1_pre_write_qualification <= A_WE_StdLogicVector ((internal_cpu_data_master_granted_sys_ram_s1 = '1'),cpu_data_master_byteenable,("1111"));
  sys_ram_s1_reset_n <= d2_reset_n;
  --vhdl renameroo for output signals
  cpu_instruction_master_requests_sys_ram_s1 <= internal_cpu_instruction_master_requests_sys_ram_s1;
  --vhdl renameroo for output signals
  d1_sys_ram_s1_end_xfer <= internal_d1_sys_ram_s1_end_xfer;
  --vhdl renameroo for output signals
  cpu_instruction_master_qualified_request_sys_ram_s1 <= internal_cpu_instruction_master_qualified_request_sys_ram_s1;
  --vhdl renameroo for output signals
  cpu_data_master_s_turn_at_sys_ram_s1 <= internal_cpu_data_master_s_turn_at_sys_ram_s1;