nios_module.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

--megafunction wizard: %Altera SOPC Builder 2.7%
--GENERATION: STANDARD
--VERSION: WM1.0

--cyclone32: nios_module.vhd
--manual changes are highlighted by '###'

--Copyright (C) 1991-2002 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only to
--program PLD devices (but not masked PLD devices) from Altera.  Any other
--use of such megafunction design, net list, support information, device
--programming or simulation file, or any other related documentation or
--information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner.  Title to
--the intellectual property, including patents, copyrights, trademarks,
--trade secrets, or maskworks, embodied in any such megafunction design,
--net list, support information, device programming or simulation file, or
--any other related documentation or information provided by Altera or a
--megafunction partner, remains with Altera, the megafunction partner, or
--their respective licensors.  No other licenses, including any licenses
--needed under any third party's intellectual property, are provided herein.
--Copying or modifying any file, or portion thereof, to which this notice
--is attached violates this copyright.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity sys_ram_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_data_master_address : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
                 signal cpu_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_data_master_read : IN STD_LOGIC;
                 signal cpu_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_data_master_write : IN STD_LOGIC;
                 signal cpu_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_instruction_master_address : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
                 signal cpu_instruction_master_flush_qualified_exported : IN STD_LOGIC;
                 signal cpu_instruction_master_latency_counter : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal cpu_instruction_master_read : IN STD_LOGIC;
                 signal d2_reset_n : IN STD_LOGIC;
                 signal sys_ram_s1_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

              -- outputs:
                 signal cpu_data_master_granted_sys_ram_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_qualified_request_sys_ram_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_read_data_valid_sys_ram_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_requests_sys_ram_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_s_turn_at_sys_ram_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_granted_sys_ram_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_sys_ram_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_read_data_valid_sys_ram_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_requests_sys_ram_s1 : OUT STD_LOGIC;
                 signal d1_cpu_data_master_granted_sys_ram_s1 : OUT STD_LOGIC;
                 signal d1_cpu_instruction_master_granted_sys_ram_s1 : OUT STD_LOGIC;
                 signal d1_sys_ram_s1_end_xfer : OUT STD_LOGIC;
                 signal registered_cpu_data_master_read_data_valid_sys_ram_s1 : OUT STD_LOGIC;
                 signal sys_ram_s1_address : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
                 signal sys_ram_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal sys_ram_s1_reset_n : OUT STD_LOGIC;
                 signal sys_ram_s1_writebyteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal sys_ram_s1_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );

attribute auto_dissolve : boolean ;
attribute auto_dissolve of sys_ram_s1_arbitrator : entity is FALSE ;
end entity sys_ram_s1_arbitrator;


architecture europa of sys_ram_s1_arbitrator is
              signal cpu_data_master_read_data_valid_sys_ram_s1_shift_register :  STD_LOGIC;
              signal cpu_data_master_read_data_valid_sys_ram_s1_shift_register_in :  STD_LOGIC;
              signal cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register :  STD_LOGIC;
              signal cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register_in :  STD_LOGIC;
              signal grant_0 :  STD_LOGIC;
              signal in_a_read_cycle :  STD_LOGIC;
              signal in_a_write_cycle :  STD_LOGIC;
              signal internal_cpu_data_master_granted_sys_ram_s1 :  STD_LOGIC;
              signal internal_cpu_data_master_qualified_request_sys_ram_s1 :  STD_LOGIC;
              signal internal_cpu_data_master_requests_sys_ram_s1 :  STD_LOGIC;
              signal internal_cpu_data_master_s_turn_at_sys_ram_s1 :  STD_LOGIC;
              signal internal_cpu_instruction_master_granted_sys_ram_s1 :  STD_LOGIC;
              signal internal_cpu_instruction_master_qualified_request_sys_ram_s1 :  STD_LOGIC;
              signal internal_cpu_instruction_master_requests_sys_ram_s1 :  STD_LOGIC;
              signal internal_d1_cpu_data_master_granted_sys_ram_s1 :  STD_LOGIC;
              signal internal_d1_cpu_instruction_master_granted_sys_ram_s1 :  STD_LOGIC;
              signal internal_d1_sys_ram_s1_end_xfer :  STD_LOGIC;
              signal next_grant_0 :  STD_LOGIC;
              signal p1_cpu_data_master_read_data_valid_sys_ram_s1_shift_register :  STD_LOGIC;
              signal p1_cpu_instruction_master_read_data_valid_sys_ram_s1_shift_register :  STD_LOGIC;
              signal sys_ram_s1_dummy_write :  STD_LOGIC;
              signal sys_ram_s1_end_xfer :  STD_LOGIC;
              signal sys_ram_s1_in_a_read_cycle :  STD_LOGIC;
              signal sys_ram_s1_in_a_write_cycle :  STD_LOGIC;
              signal sys_ram_s1_waits_for_read :  STD_LOGIC;
              signal sys_ram_s1_waits_for_write :  STD_LOGIC;
              signal sys_ram_s1_writebyteenable_sys_ram_s1_pre_write_qualification :  STD_LOGIC_VECTOR (3 DOWNTO 0);
              signal wait_for_sys_ram_s1_counter :  STD_LOGIC;

begin

  --cpu_data_master_granted_sys_ram_s1 granted, which is an e_assign
  internal_cpu_data_master_granted_sys_ram_s1 <= internal_cpu_data_master_qualified_request_sys_ram_s1 AND ((NOT internal_cpu_instruction_master_qualified_request_sys_ram_s1 OR ((A_WE_StdLogic ((internal_d1_sys_ram_s1_end_xfer = '1'),internal_cpu_data_master_s_turn_at_sys_ram_s1,internal_d1_cpu_data_master_granted_sys_ram_s1)))));
  --cpu_instruction_master_granted_sys_ram_s1 granted, which is an e_assign
  internal_cpu_instruction_master_granted_sys_ram_s1 <= internal_cpu_instruction_master_qualified_request_sys_ram_s1 AND ((NOT internal_cpu_data_master_qualified_request_sys_ram_s1 OR ((A_WE_StdLogic ((internal_d1_sys_ram_s1_end_xfer = '1'),(NOT internal_cpu_data_master_s_turn_at_sys_ram_s1),internal_d1_cpu_instruction_master_granted_sys_ram_s1)))));
  internal_cpu_data_master_requests_sys_ram_s1 <= to_std_logic(((cpu_data_master_address(20 DOWNTO 8) & "00000000") = "000000000010000000000")) AND ((cpu_data_master_read OR cpu_data_master_write));
  --assign sys_ram_s1_readdata_from_sa = sys_ram_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  sys_ram_s1_readdata_from_sa <= sys_ram_s1_readdata;
  --registered rdv signal_name registered_cpu_data_master_read_data_valid_sys_ram_s1 assignment, which is an e_assign
  registered_cpu_data_master_read_data_valid_sys_ram_s1 <= cpu_data_master_read_data_valid_sys_ram_s1_shift_register_in;
  internal_cpu_data_master_qualified_request_sys_ram_s1 <= internal_cpu_data_master_requests_sys_ram_s1 AND NOT ((((cpu_data_master_read AND (cpu_data_master_read_data_valid_sys_ram_s1_shift_register))) OR (((NOT cpu_data_master_waitrequest) AND cpu_data_master_write))));
  cpu_data_master_read_data_valid_sys_ram_s1_shift_register_in <= ((internal_cpu_data_master_granted_sys_ram_s1 AND cpu_data_master_read) AND NOT sys_ram_s1_waits_for_read) AND NOT (cpu_data_master_read_data_valid_sys_ram_s1_shift_register);
  p1_cpu_data_master_read_data_valid_sys_ram_s1_shift_register <= Vector_To_Std_Logic(Std_Logic_Vector'(A_ToStdLogicVector(cpu_data_master_read_data_valid_sys_ram_s1_shift_register) & A_ToStdLogicVector(cpu_data_master_read_data_valid_sys_ram_s1_shift_register_in)));
  process (clk, d2_reset_n)
  begin
    if d2_reset_n = '0' then