cyclone32.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

-- cyclone32 top entity
-- forms a wrapper around the nios_module

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cyclone32 is

port (
	clk		: in std_logic;
--
---- serial interface
--
	ser_txd			: out std_logic;
	ser_rxd			: in std_logic;
	ser_ncts		: in std_logic;
	ser_nrts		: out std_logic;

--
--	watchdog
--
	wd		: out std_logic;
	freeio	: out std_logic;

--
--	two ram banks
--
	rama_a		: out std_logic_vector(17 downto 0);
	rama_d		: inout std_logic_vector(15 downto 0);
	rama_ncs	: out std_logic;
	rama_noe	: out std_logic;
	rama_nlb	: out std_logic;
	rama_nub	: out std_logic;
	rama_nwe	: out std_logic;
	ramb_a		: out std_logic_vector(17 downto 0);
	ramb_d		: inout std_logic_vector(15 downto 0);
	ramb_ncs	: out std_logic;
	ramb_noe	: out std_logic;
	ramb_nlb	: out std_logic;
	ramb_nub	: out std_logic;
	ramb_nwe	: out std_logic;

--
--	config/program flash and big nand flash
--
	fl_a	: out std_logic_vector(18 downto 0);
	fl_d	: inout std_logic_vector(7 downto 0);
	fl_ncs	: out std_logic;
	fl_ncsb	: out std_logic;
	fl_noe	: out std_logic;
	fl_nwe	: out std_logic;
	fl_rdy	: in std_logic;

--
--	I/O pins of board
--
	io_b	: inout std_logic_vector(10 downto 1);
	io_l	: inout std_logic_vector(20 downto 1);
	io_r	: inout std_logic_vector(20 downto 1);
	io_t	: inout std_logic_vector(6 downto 1);
--
--	dummy input pins for EP1C6 on board with EP1C12 pinout
--	EP1C12 has additional GND and VCCINT pins.
--
	dummy_gnd		: out std_logic_vector(5 downto 0);
	dummy_vccint	: out std_logic_vector(5 downto 0)
);
end cyclone32;

architecture wrapper of cyclone32 is

--
--	components:
--

component nios_module is
        port (
              -- global signals:
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

    		  -- interface to the ext_ram
                 signal select0_n_to_the_ext_ram : OUT STD_LOGIC;
                 signal select1_n_to_the_ext_ram : OUT STD_LOGIC;
                 signal tri_state_bridge_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
                 signal tri_state_bridge_byteenablen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal tri_state_bridge_data : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal tri_state_bridge_readn : OUT STD_LOGIC;
                 signal write_n_to_the_ext_ram : OUT STD_LOGIC;

              -- the_uart
                 signal rxd_to_the_uart : IN STD_LOGIC;
                 signal txd_from_the_uart : OUT STD_LOGIC;

              -- the_watchdog_pio
                 signal out_port_from_the_watchdog_pio : OUT STD_LOGIC
              );
end component nios_module;

--
-- Signals
--
signal internal_clk : STD_LOGIC;
signal internal_reset_n : STD_LOGIC;
signal internal_rama_ncs : STD_LOGIC;
signal internal_ramb_ncs : STD_LOGIC;
signal internal_ram_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal internal_ram_byteenablen : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_ram_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_ram_noe : STD_LOGIC;
signal internal_ram_nwe : STD_LOGIC;
signal internal_rxd : STD_LOGIC;
signal internal_txd : STD_LOGIC;
signal internal_wd : STD_LOGIC;

	signal int_res			: std_logic;
	signal res_cnt			: unsigned(2 downto 0);

begin

--
-- The NIOS module
--

the_nios_module : nios_module
   port map (
     clk => internal_clk,
     reset_n => internal_reset_n,

     -- interface to the ext_ram
     select0_n_to_the_ext_ram => internal_rama_ncs,
     select1_n_to_the_ext_ram => internal_ramb_ncs,
     tri_state_bridge_address => internal_ram_address,
     tri_state_bridge_byteenablen => internal_ram_byteenablen,
     tri_state_bridge_data => internal_ram_data,
     tri_state_bridge_readn => internal_ram_noe,
     write_n_to_the_ext_ram => internal_ram_nwe,

     -- the_uart
     rxd_to_the_uart => internal_rxd,
     txd_from_the_uart => internal_txd,

     -- the_watchdog_pio
     out_port_from_the_watchdog_pio => internal_wd
     
   );

--
--	intern reset
--	no extern reset, epm7064 has too less pins
--

process(clk)
begin
	if rising_edge(clk) then
		if (res_cnt/="111") then
			res_cnt <= res_cnt+1;
		end if;

		int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2);
	end if;
end process;

internal_clk <= clk;
internal_reset_n <= not int_res;
rama_ncs <= internal_rama_ncs;
ramb_ncs <= internal_ramb_ncs;
rama_a <= internal_ram_address(19 DOWNTO 2);
ramb_a <= internal_ram_address(19 DOWNTO 2);
rama_nlb <= internal_ram_byteenablen(0);
rama_nub <= internal_ram_byteenablen(1);
ramb_nlb <= internal_ram_byteenablen(2);
ramb_nub <= internal_ram_byteenablen(3);
rama_d <= internal_ram_data(15 DOWNTO 0);
ramb_d <= internal_ram_data(31 DOWNTO 16);
internal_ram_data(15 DOWNTO 0) <= rama_d;
internal_ram_data(31 DOWNTO 16)<= ramb_d;
rama_noe <= internal_ram_noe;
ramb_noe <= internal_ram_noe;
rama_nwe <= internal_ram_nwe;
ramb_nwe <= internal_ram_nwe;
ser_txd <= internal_txd;
internal_rxd <= ser_rxd;
wd <= internal_wd;

--
--	config/program flash and big nand flash
--  ### not used ###
	fl_a	<= (others => 'Z');
	fl_d	<= (others => 'Z');
	fl_ncs	<= 'Z';
	fl_ncsb	<= 'Z';
	fl_noe	<= 'Z';
	fl_nwe	<= 'Z';
--	fl_rdy	-- ### input ignored ###

--
--	I/O pins of board
--  ### not used ###
	io_b <= (others => 'Z');
	io_l <= (others => 'Z');
	io_r <= (others => 'Z');
	io_t <= (others => 'Z');
--
---- serial interface
--
--	ser_ncts -- ### input ignored ###
	ser_nrts <= '0';		-- default RTS if HW handshake is used on PC

--
--	EP1C12 additional power pins as tristated output on EP1C6
--
	dummy_gnd <= (others => 'Z');
	dummy_vccint <= (others => 'Z');
	freeio <= 'Z';

end wrapper;