usr0_cpu.vhd

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--Copyright (C) 1991-2002 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only to
--program PLD devices (but not masked PLD devices) from Altera.  Any other
--use of such megafunction design, net list, support information, device
--programming or simulation file, or any other related documentation or
--information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner.  Title to
--the intellectual property, including patents, copyrights, trademarks,
--trade secrets, or maskworks, embodied in any such megafunction design,
--net list, support information, device programming or simulation file, or
--any other related documentation or information provided by Altera or a
--megafunction partner, remains with Altera, the megafunction partner, or
--their respective licensors.  No other licenses, including any licenses
--needed under any third party's intellectual property, are provided herein.
--Copying or modifying any file, or portion thereof, to which this notice
--is attached violates this copyright.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity USR0_cpu is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clk_en : IN STD_LOGIC;
                 signal dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset : IN STD_LOGIC;
                 signal start : IN STD_LOGIC;

              -- outputs:
                 signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );

end entity USR0_cpu;


architecture europa of USR0_cpu is
              signal absolute_a :  STD_LOGIC_VECTOR (31 DOWNTO 0);
              signal b :  STD_LOGIC_VECTOR (31 DOWNTO 0);
              signal b_into_adder :  STD_LOGIC_VECTOR (31 DOWNTO 0);
              signal carry :  STD_LOGIC;
              signal dataa_is_negative :  STD_LOGIC;
              signal datab_is_negative :  STD_LOGIC;
              signal datab_was_negative :  STD_LOGIC;
              signal negate :  STD_LOGIC;
              signal p1_q :  STD_LOGIC_VECTOR (65 DOWNTO 0);
              signal p1_subtract :  STD_LOGIC;
              signal q :  STD_LOGIC_VECTOR (65 DOWNTO 0);
              signal reset_n :  STD_LOGIC;
              signal subtract :  STD_LOGIC;
              signal sum :  STD_LOGIC_VECTOR (32 DOWNTO 0);

begin

  reset_n <= NOT reset;
  dataa_is_negative <= dataa(31);
  datab_is_negative <= datab(31);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      datab_was_negative <= '0';
    elsif clk'event and clk = '1' then
      if (((clk_en AND start))) = '1' then 
        datab_was_negative <= datab_is_negative;
      end if;
    end if;

  end process;

  absolute_a <= A_WE_StdLogicVector ((dataa_is_negative = '1'),("00000000000000000000000000000000" - dataa),dataa);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      b <= "00000000000000000000000000000000";
    elsif clk'event and clk = '1' then
      if (((clk_en AND start))) = '1' then 
        b <= datab;
      end if;
    end if;

  end process;

  p1_subtract <= A_WE_StdLogic ((start = '1'),(NOT datab_is_negative),((carry XOR datab_was_negative)));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      subtract <= '0';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        subtract <= p1_subtract;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      negate <= '0';
    elsif clk'event and clk = '1' then
      if (((clk_en AND start))) = '1' then 
        negate <= dataa_is_negative XOR datab_is_negative;
      end if;
    end if;

  end process;

  p1_q <= A_WE_StdLogicVector ((start = '1'),Std_Logic_Vector'(A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & A_ToStdLogicVector('0') & absolute_a(31 DOWNTO 0)),(sum(32 DOWNTO 0) & q(31 DOWNTO 0) & A_ToStdLogicVector(carry)));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      q <= "000000000000000000000000000000000000000000000000000000000000000000";
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        q <= p1_q;
      end if;
    end if;

  end process;

  b_into_adder <= A_WE_StdLogicVector ((subtract = '1'),("00000000000000000000000000000000" - b),b);
  (carry, sum(32), sum(31), sum(30), sum(29), sum(28), sum(27), sum(26), sum(25), sum(24), sum(23), sum(22), sum(21), sum(20), sum(19), sum(18), sum(17), sum(16), sum(15), sum(14), sum(13), sum(12), sum(11), sum(10), sum(9), sum(8), sum(7), sum(6), sum(5), sum(4), sum(3), sum(2), sum(1), sum(0)) <= Std_Logic_Vector'(A_ToStdLogicVector('0') & q(64 DOWNTO 32)) + Std_Logic_Vector'(A_ToStdLogicVector('0') & A_ToStdLogicVector(b_into_adder(31)) & b_into_adder(31 DOWNTO 0));
  result <= A_WE_StdLogicVector ((negate = '1'),("00000000000000000000000000000000" - q(31 DOWNTO 0)),q(31 DOWNTO 0));

end europa;